Imagen de Portada

Hiding in Plain Sight: Reframing Hardware Trojan Benchmarking as a Hide&Seek Modification

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Sarihi, Amin, Patooghy, Ahmad, Jamieson, Peter, Badawy, Abdel-Hameed A.
Formato:	Preprint
Publicado:	2024
Materias:	Cryptography and Security Hardware Architecture Machine Learning B.8.1
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

Trojan Playground: A Reinforcement Learning Framework for Hardware Trojan Insertion and Detection
por: Sarihi, Amin, et al.
Publicado: (2023)

The Seeker's Dilemma: Realistic Formulation and Benchmarking for Hardware Trojan Detection
por: Sarihi, Amin, et al.
Publicado: (2024)

TrojanForge: Generating Adversarial Hardware Trojan Examples Using Reinforcement Learning
por: Sarihi, Amin, et al.
Publicado: (2024)

iThermTroj: Exploiting Intermittent Thermal Trojans in Multi-Processor System-on-Chips
por: Elahi, Mehdi, et al.
Publicado: (2025)

MATTER: Multi-stage Adaptive Thermal Trojan for Efficiency & Resilience degradation
por: Elahi, Mehdi, et al.
Publicado: (2024)

TrojanWhisper: Evaluating Pre-trained LLMs to Detect and Localize Hardware Trojans
por: Faruque, Md Omar, et al.
Publicado: (2024)

Unleashing GHOST: An LLM-Powered Framework for Automated Hardware Trojan Design
por: Faruque, Md Omar, et al.
Publicado: (2024)

BackCache: Mitigating Contention-Based Cache Timing Attacks by Hiding Cache Line Evictions
por: Wang, Quancheng, et al.
Publicado: (2023)

TroLL: Exploiting Structural Similarities between Logic Locking and Hardware Trojans
por: Liu, Yuntao, et al.
Publicado: (2023)

SCARF: Securing Chips with a Robust Framework against Fabrication-time Hardware Trojans
por: Eslami, Mohammad, et al.
Publicado: (2024)

TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
por: Sreekumar, Saideep, et al.
Publicado: (2026)

Evasive Hardware Trojan through Adversarial Power Trace
por: Omidi, Behnam, et al.
Publicado: (2024)

ROSGuard: A Bandwidth Regulation Mechanism for ROS2-based Applications
por: Puente, Jon Altonaga, et al.
Publicado: (2025)

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
por: Wang, Fangzhou, et al.
Publicado: (2024)

Trojan-Resilient NTT: Protecting Against Control Flow and Timing Faults on Reconfigurable Platforms
por: Paul, Rourab, et al.
Publicado: (2026)

Hiding in Plain Sight: An IoT Traffic Camouflage Framework for Enhanced Privacy
por: Worae, Daniel Adu, et al.
Publicado: (2025)

Security Properties for Open-Source Hardware Designs
por: Rogers, Jayden, et al.
Publicado: (2024)

FARe: Fault-Aware GNN Training on ReRAM-based PIM Accelerators
por: Dhingra, Pratyush, et al.
Publicado: (2024)

Efficient and Lightweight In-memory Computing Architecture for Hardware Security
por: Ajmi, Hala, et al.
Publicado: (2022)

Modern Hardware Security: A Review of Attacks and Countermeasures
por: Mishra, Jyotiprakash, et al.
Publicado: (2025)

Bridging the Gap between Hardware Fuzzing and Industrial Verification
por: Ma, Ruiyang, et al.
Publicado: (2025)

Presto: Hardware Acceleration of Ciphers for Hybrid Homomorphic Encryption
por: Jeon, Yeonsoo, et al.
Publicado: (2025)

Secure Software/Hardware Hybrid In-Field Testing for System-on-Chip
por: Mulhem, Saleh, et al.
Publicado: (2024)

RedMulE-FT: A Reconfigurable Fault-Tolerant Matrix Multiplication Engine
por: Wiese, Philip, et al.
Publicado: (2025)

High-Security Hardware Module with PUF and Hybrid Cryptography for Data Security
por: Amael, Joshua Tito, et al.
Publicado: (2024)

Per-Row Activation Counting on Real Hardware: Demystifying Performance Overheads
por: Kim, Jumin, et al.
Publicado: (2025)

Palermo: Improving the Performance of Oblivious Memory using Protocol-Hardware Co-Design
por: Ye, Haojie, et al.
Publicado: (2024)

AMAZE: Accelerated MiMC Hardware Architecture for Zero-Knowledge Applications on the Edge
por: Ahmed, Anees, et al.
Publicado: (2024)

Towards Closing the Performance Gap for Cryptographic Kernels Between CPUs and Specialized Hardware
por: Zhang, Naifeng, et al.
Publicado: (2025)

Efficient Hardware Implementation of Modular Multiplier over GF (2m) on FPGA
por: Kumari, Ruby, et al.
Publicado: (2025)

An Efficient Algorithm for Modulus Operation and Its Hardware Implementation in Prime Number Calculation
por: Wijesinghe, W. A. Susantha
Publicado: (2024)

"vcd2df" -- Leveraging Data Science Insights for Hardware Security Research
por: Deutschbein, Calvin, et al.
Publicado: (2025)

Enabling Deterministic User-Level Interrupts in Real-Time Processors via Hardware Extension
por: Yang, Hongbin, et al.
Publicado: (2026)

ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
por: Ku, Jonathan, et al.
Publicado: (2024)

An FPGA-Based Open-Source Hardware-Software Framework for Side-Channel Security Research
por: Zoni, Davide, et al.
Publicado: (2024)

QTFlow: Quantitative Timing-Sensitive Information Flow for Security-Aware Hardware Design on RTL
por: Reimann, Lennart M., et al.
Publicado: (2024)

REDACTOR: eFPGA Redaction for DNN Accelerator Security
por: Baddour, Yazan, et al.
Publicado: (2025)

RTL2M$μ$PATH: Multi-$μ$PATH Synthesis with Applications to Hardware Security Verification
por: Hsiao, Yao, et al.
Publicado: (2024)

Hardware-Friendly Randomization: Enabling Random-Access and Minimal Wiring in FHE Accelerators with Low Total Cost
por: Rosenfeld, Ilan, et al.
Publicado: (2026)

History-Aware Trajectory k-Anonymization Using an FPGA-Based Hardware Accelerator for Real-Time Location Services
por: Nakano, Hiroshi, et al.
Publicado: (2025)