Design of a 64-bit SQRT-CSLA with Reduced Area and High-Speed Applications in Low Power VLSI Circuits
Fuente:
arXiv
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| Auteurs principaux: | Pallavi, CH., Padma, C., Kumar, R. Kiran, Suguna, T., Nalini, C. |
|---|---|
| Format: | Preprint |
| Publié: |
2024
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