Formalising CXL Cache Coherence
Fuente:
arXiv
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| Autori principali: | , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866915204010344448 |
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| author | Tan, Chengsong Donaldson, Alastair F. Wickerson, John |
| author_facet | Tan, Chengsong Donaldson, Alastair F. Wickerson, John |
| contents | We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English specification. This led to us identifying and proposing fixes to several problems we identified as unclear, ambiguous or inaccurate, some of which could lead to incoherence if left unfixed. Nearly all our issues and proposed fixes have been confirmed and tentatively accepted by the CXL consortium for adoption, save for one which is still under discussion. To validate the faithfulness of our model we performed scenario verification of essential restrictions such as "Snoop-pushes-GO", and produced a fully mechanised proof of a coherence property of the model. The considerable size of this proof, comprising tens of thousands of lemmas, prompted us to develop new proof automation tools, which we have made available for other Isabelle users working with similarly cumbersome proofs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_15908 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Formalising CXL Cache Coherence Tan, Chengsong Donaldson, Alastair F. Wickerson, John Hardware Architecture Programming Languages 68 (Primary) C.1; F.3 We report our experience formally modelling and verifying CXL.cache, the inter-device cache coherence protocol of the Compute Express Link standard. We have used the Isabelle proof assistant to create a formal model for CXL.cache based on the prose English specification. This led to us identifying and proposing fixes to several problems we identified as unclear, ambiguous or inaccurate, some of which could lead to incoherence if left unfixed. Nearly all our issues and proposed fixes have been confirmed and tentatively accepted by the CXL consortium for adoption, save for one which is still under discussion. To validate the faithfulness of our model we performed scenario verification of essential restrictions such as "Snoop-pushes-GO", and produced a fully mechanised proof of a coherence property of the model. The considerable size of this proof, comprising tens of thousands of lemmas, prompted us to develop new proof automation tools, which we have made available for other Isabelle users working with similarly cumbersome proofs. |
| title | Formalising CXL Cache Coherence |
| topic | Hardware Architecture Programming Languages 68 (Primary) C.1; F.3 |
| url | https://arxiv.org/abs/2410.15908 |