ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package
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arXiv
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| Autori principali: | , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866911103097765888 |
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| author | Ottaviano, Alessandro Balas, Robert Fischer, Tim Benz, Thomas Bartolini, Andrea Benini, Luca |
| author_facet | Ottaviano, Alessandro Balas, Robert Fischer, Tim Benz, Thomas Bartolini, Andrea Benini, Luca |
| contents | The growing complexity of real-time control algorithms with increasing performance demands, along with the shift to 2.5D technology, drive the need for scalable controllers to manage chiplets' coupled operation in 2.5D systems-in-package. These controllers must offer real-time computing capabilities, as well as System-in-package (SiP) compatible IO interfaces for communicating with the controlled dies. Due to real-time constraints, a key challenge is minimizing the performance penalty of die-to-die communication with respect to native on-chip control interfaces. We address this challenge with ControlPULPlet, an open-source, real-time multi-core RISC-V controller designed specifically for SiP integration. ControlPULPlet features a 32-bit CV32RT core for fast interrupt handling and a specialized direct memory access engine to automate periodic sensor readout. A tightly-coupled programmable multi-core cluster for acceleration of advanced control algorithms is integrated through a dedicated AXI4 port. A flexible AXI4-compatible die-to-die (D2D) link enables efficient communication in 2.5D SiPs. We implemented and fabricated ControlPULPlet as a silicon demonstrator called Kairos in TSMC's 65nm CMOS. Kairos runs model predictive control algorithms at up to 290 MHz in a 30 mW power envelope. The D2D link attains a peak duplex transfer rate of 51 Gbit/s at 200 MHz, at the minimal costs of just 7.6 kGE in PHY area per channel, adding just 2.9% to the total system area. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_15985 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package Ottaviano, Alessandro Balas, Robert Fischer, Tim Benz, Thomas Bartolini, Andrea Benini, Luca Hardware Architecture The growing complexity of real-time control algorithms with increasing performance demands, along with the shift to 2.5D technology, drive the need for scalable controllers to manage chiplets' coupled operation in 2.5D systems-in-package. These controllers must offer real-time computing capabilities, as well as System-in-package (SiP) compatible IO interfaces for communicating with the controlled dies. Due to real-time constraints, a key challenge is minimizing the performance penalty of die-to-die communication with respect to native on-chip control interfaces. We address this challenge with ControlPULPlet, an open-source, real-time multi-core RISC-V controller designed specifically for SiP integration. ControlPULPlet features a 32-bit CV32RT core for fast interrupt handling and a specialized direct memory access engine to automate periodic sensor readout. A tightly-coupled programmable multi-core cluster for acceleration of advanced control algorithms is integrated through a dedicated AXI4 port. A flexible AXI4-compatible die-to-die (D2D) link enables efficient communication in 2.5D SiPs. We implemented and fabricated ControlPULPlet as a silicon demonstrator called Kairos in TSMC's 65nm CMOS. Kairos runs model predictive control algorithms at up to 290 MHz in a 30 mW power envelope. The D2D link attains a peak duplex transfer rate of 51 Gbit/s at 200 MHz, at the minimal costs of just 7.6 kGE in PHY area per channel, adding just 2.9% to the total system area. |
| title | ControlPULPlet: A Flexible Real-time Multi-core RISC-V Controller for 2.5D Systems-in-package |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2410.15985 |