A 0.03${mm}^2$ 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing
Fuente:
arXiv
Salvato in:
| Autori principali: | , , |
|---|---|
| Natura: | Preprint |
| Pubblicazione: |
2024
|
| Soggetti: | |
| Accesso online: | |
| Tags: |
Aggiungi Tag
Nessun Tag, puoi essere il primo ad aggiungerne!!
|
| _version_ | 1866909358749646848 |
|---|---|
| author | Ray, Yudhajit Ghosh, Archisman Sen, Shreyas |
| author_facet | Ray, Yudhajit Ghosh, Archisman Sen, Shreyas |
| contents | Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and accurate clock generation are of the utmost importance. This paper presents a unique implementation of integrating sub-sampling phase locked loop, which alleviates the usage of additional gain elements in the PLL and reduces the noise injection in the system. In this design, the ring oscillator-based PLL can operate a wide frequency range of 100-250MHz while consuming 0.03mm2 of area and 131.8$μW$ of power at 250MHz. The area-normalized figure of merit (FOM) of the integrating SSPLL is found to be -236, while showing a reference spur of -43.2dB. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_16310 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | A 0.03${mm}^2$ 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing Ray, Yudhajit Ghosh, Archisman Sen, Shreyas Signal Processing Hardware Architecture Clock generation is an essential part of wireless or wireline communication modules. To facilitate recent advancements in wireline-like communication and in-sensor computing modules at relatively lower data rates, ultra-low power, and accurate clock generation are of the utmost importance. This paper presents a unique implementation of integrating sub-sampling phase locked loop, which alleviates the usage of additional gain elements in the PLL and reduces the noise injection in the system. In this design, the ring oscillator-based PLL can operate a wide frequency range of 100-250MHz while consuming 0.03mm2 of area and 131.8$μW$ of power at 250MHz. The area-normalized figure of merit (FOM) of the integrating SSPLL is found to be -236, while showing a reference spur of -43.2dB. |
| title | A 0.03${mm}^2$ 100-250MHz Charge-Pump or Amplifier-Less Integrating Sub-Sampling PLL for Ultra-low Power Communication and Computing |
| topic | Signal Processing Hardware Architecture |
| url | https://arxiv.org/abs/2410.16310 |