Towards Efficient IMC Accelerator Design Through Joint Hardware-Workload Co-optimization
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arXiv
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| Main Authors: | Krestinskaya, Olga, Fouda, Mohammed E., Eltawil, Ahmed, Salama, Khaled N. |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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