Statistical Analysis of Spurious Dot Formation in SiMOS Single Electron Transistors

Fuente: arXiv
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Hauptverfasser: Chen, Kuan-Chu, Godfrin, Clement, Simion, George, Fattal, Imri, Kubicek, Stefan, Beyne, Sofie, Raes, Bart, Loenders, Arne, Kao, Kuo-Hsing, Wan, Danny, De Greve, Kristiaan
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Veröffentlicht: 2024
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author Chen, Kuan-Chu
Godfrin, Clement
Simion, George
Fattal, Imri
Kubicek, Stefan
Beyne, Sofie
Raes, Bart
Loenders, Arne
Kao, Kuo-Hsing
Wan, Danny
De Greve, Kristiaan
author_facet Chen, Kuan-Chu
Godfrin, Clement
Simion, George
Fattal, Imri
Kubicek, Stefan
Beyne, Sofie
Raes, Bart
Loenders, Arne
Kao, Kuo-Hsing
Wan, Danny
De Greve, Kristiaan
contents The spatial distribution of spurious dots in SiMOS single-electron transistors (SETs), fabricated on an industrial 300 mm process line, has been statistically analyzed. To have a deeper understanding of the origin of these spurious dots, we analyzed SETs with three different oxide thicknesses: 8 nm, 12 nm and 20 nm. By combining spurious dot triangulation cryo-measurement with simulations of strain, gate bias, and location of the electron wave function, we demonstrate that most spurious dots are formed through the combined effects of strain and gate bias, leading to variations in the conduction band energy. Despite the similar thermal expansion coefficients of polycrystalline silicon gates and single-crystalline silicon substrates, strain remains a crucial factor in spurious dots formation. This learning can be use to optimize the device design and the oxide thickness, to reduce the density of spurious dot while keeping quantum dot tunability.
format Preprint
id arxiv_https___arxiv_org_abs_2410_18546
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Statistical Analysis of Spurious Dot Formation in SiMOS Single Electron Transistors
Chen, Kuan-Chu
Godfrin, Clement
Simion, George
Fattal, Imri
Kubicek, Stefan
Beyne, Sofie
Raes, Bart
Loenders, Arne
Kao, Kuo-Hsing
Wan, Danny
De Greve, Kristiaan
Mesoscale and Nanoscale Physics
The spatial distribution of spurious dots in SiMOS single-electron transistors (SETs), fabricated on an industrial 300 mm process line, has been statistically analyzed. To have a deeper understanding of the origin of these spurious dots, we analyzed SETs with three different oxide thicknesses: 8 nm, 12 nm and 20 nm. By combining spurious dot triangulation cryo-measurement with simulations of strain, gate bias, and location of the electron wave function, we demonstrate that most spurious dots are formed through the combined effects of strain and gate bias, leading to variations in the conduction band energy. Despite the similar thermal expansion coefficients of polycrystalline silicon gates and single-crystalline silicon substrates, strain remains a crucial factor in spurious dots formation. This learning can be use to optimize the device design and the oxide thickness, to reduce the density of spurious dot while keeping quantum dot tunability.
title Statistical Analysis of Spurious Dot Formation in SiMOS Single Electron Transistors
topic Mesoscale and Nanoscale Physics
url https://arxiv.org/abs/2410.18546