Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2410.20241 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866912613857755136 |
|---|---|
| author | Prajapati, Tomis Mehta, Harsh Banerjee, Shreya Panigrahi, Prasanta K. Narayanan, V. |
| author_facet | Prajapati, Tomis Mehta, Harsh Banerjee, Shreya Panigrahi, Prasanta K. Narayanan, V. |
| contents | Violation of the Bell-type inequalities is necessary to confirm the existence of nonlocality in nonclassical (entangled) states. We have designed a customized operator which is made of the sum of the Pauli matrices ($σ_x$, $σ_y$, and $σ_z$). We theoretically and experimentally investigate the violation of Bell-type inequalities using two- and four-qubit Dicke states on IBM Quantum Processing Units (QPUs). We compare two different state preparation methods for the four-qubit Dicke state -- gate-based and statevector-based -- and evaluate their performance on two IBM QPUs, \texttt{ibm\_kyiv} and \texttt{ibm\_sherbrook}. For the two-qubit case, we demonstrate clear violations of the CHSH inequality, with the highest observed Bell parameter reaching $2.821 \pm 0.0019$ using M3 error mitigation, which is within $0.7σ$ of the theoretical maximum $2\sqrt{2}$. In the four-qubit case, we employ a Bell-type inequality tailored for Dicke states and achieve a maximum violation of $2.607 \pm 0.029$ without the need for additional mitigation when using the statevector-based method. Our results reveal that advanced error mitigation techniques significantly enhance the observed violations in the gate-based method, while the statevector-based approach inherently yields more robust states with lower noise. This study highlights the critical role of state preparation and mitigation techniques in probing fundamental quantum correlations on near-term quantum hardware. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_20241 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Experimental demonstration of the Bell-type inequalities for four qubit Dicke state using IBM Quantum Processing Units Prajapati, Tomis Mehta, Harsh Banerjee, Shreya Panigrahi, Prasanta K. Narayanan, V. Quantum Physics Violation of the Bell-type inequalities is necessary to confirm the existence of nonlocality in nonclassical (entangled) states. We have designed a customized operator which is made of the sum of the Pauli matrices ($σ_x$, $σ_y$, and $σ_z$). We theoretically and experimentally investigate the violation of Bell-type inequalities using two- and four-qubit Dicke states on IBM Quantum Processing Units (QPUs). We compare two different state preparation methods for the four-qubit Dicke state -- gate-based and statevector-based -- and evaluate their performance on two IBM QPUs, \texttt{ibm\_kyiv} and \texttt{ibm\_sherbrook}. For the two-qubit case, we demonstrate clear violations of the CHSH inequality, with the highest observed Bell parameter reaching $2.821 \pm 0.0019$ using M3 error mitigation, which is within $0.7σ$ of the theoretical maximum $2\sqrt{2}$. In the four-qubit case, we employ a Bell-type inequality tailored for Dicke states and achieve a maximum violation of $2.607 \pm 0.029$ without the need for additional mitigation when using the statevector-based method. Our results reveal that advanced error mitigation techniques significantly enhance the observed violations in the gate-based method, while the statevector-based approach inherently yields more robust states with lower noise. This study highlights the critical role of state preparation and mitigation techniques in probing fundamental quantum correlations on near-term quantum hardware. |
| title | Experimental demonstration of the Bell-type inequalities for four qubit Dicke state using IBM Quantum Processing Units |
| topic | Quantum Physics |
| url | https://arxiv.org/abs/2410.20241 |