Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866912089341165568 |
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| author | Devadze, Sergei Nielsen, Christine Elizabeth Mihhailov, Dmitri Ellervee, Peeter |
| author_facet | Devadze, Sergei Nielsen, Christine Elizabeth Mihhailov, Dmitri Ellervee, Peeter |
| contents | The planned high-luminosity upgrade of the Large Hadron Collider (LHC) at CERN will bring much higher data rates that are far above the capabilities of currently installed software-based data processing systems. Therefore, new methods must be used to facilitate on-the-fly extraction of scientifically significant information from the immense flow of data produced by LHC particle detectors. This paper focuses on implementation of a tau lepton triggering algorithm in FPGA. Due to the algorithm's complexity and strict technical requirements, its implementation in FPGA fabric becomes a particularly challenging task. The paper presents a study of algorithm development with the help of High-Level Synthesis (HLS) technique that can generate hardware description from C++ code. Various architectural solutions and optimizations that were tried out during the design architecture exploration process are also discussed in the paper. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2410_20430 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis Devadze, Sergei Nielsen, Christine Elizabeth Mihhailov, Dmitri Ellervee, Peeter Hardware Architecture Instrumentation and Detectors The planned high-luminosity upgrade of the Large Hadron Collider (LHC) at CERN will bring much higher data rates that are far above the capabilities of currently installed software-based data processing systems. Therefore, new methods must be used to facilitate on-the-fly extraction of scientifically significant information from the immense flow of data produced by LHC particle detectors. This paper focuses on implementation of a tau lepton triggering algorithm in FPGA. Due to the algorithm's complexity and strict technical requirements, its implementation in FPGA fabric becomes a particularly challenging task. The paper presents a study of algorithm development with the help of High-Level Synthesis (HLS) technique that can generate hardware description from C++ code. Various architectural solutions and optimizations that were tried out during the design architecture exploration process are also discussed in the paper. |
| title | Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis |
| topic | Hardware Architecture Instrumentation and Detectors |
| url | https://arxiv.org/abs/2410.20430 |