Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks
Fuente:
arXiv
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866914997623324672 |
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| author | Raja, Tejas |
| author_facet | Raja, Tejas |
| contents | The paper discusses how Systolic Arrays can improve matrix multiplication for deep neural networks (DNNs). With AI models like OpenAI's GPT now containing trillions of parameters, the need for efficient matrix multiplication is more critical than ever. In this paper, the three main systolic array data flows: Weight Stationary (WS), Input Stationary (IS), and Output Stationary (OS) are discussed. Each data flow's energy consumption and efficiency across various matrix sizes are calculated using the SCALE-Sim simulator. The results show that selecting the right data flow for specific matrix configurations can drastically reduce energy consumption. The conclusions provide helpful insights into optimizing hardware for AI and machine learning applications, offering potential improvements in designing energy-efficient DNN accelerators. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2410_22595 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks Raja, Tejas Hardware Architecture The paper discusses how Systolic Arrays can improve matrix multiplication for deep neural networks (DNNs). With AI models like OpenAI's GPT now containing trillions of parameters, the need for efficient matrix multiplication is more critical than ever. In this paper, the three main systolic array data flows: Weight Stationary (WS), Input Stationary (IS), and Output Stationary (OS) are discussed. Each data flow's energy consumption and efficiency across various matrix sizes are calculated using the SCALE-Sim simulator. The results show that selecting the right data flow for specific matrix configurations can drastically reduce energy consumption. The conclusions provide helpful insights into optimizing hardware for AI and machine learning applications, offering potential improvements in designing energy-efficient DNN accelerators. |
| title | Systolic Array Data Flows for Efficient Matrix Multiplication in Deep Neural Networks |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2410.22595 |