Hybrid cat-transmon architecture for scalable, hardware-efficient quantum error correction

Fuente: arXiv
Guardado en:
Detalles Bibliográficos
Autores principales: Hann, Connor T., Noh, Kyungjoo, Putterman, Harald, Matheny, Matthew H., Iverson, Joseph K., Fang, Michael T., Chamberland, Christopher, Painter, Oskar, Brandão, Fernando G. S. L.
Formato: Preprint
Publicado: 2024
Materias:
Acceso en línea:
Etiquetas: Agregar Etiqueta
Sin Etiquetas, Sea el primero en etiquetar este registro!
_version_ 1866915584009043968
author Hann, Connor T.
Noh, Kyungjoo
Putterman, Harald
Matheny, Matthew H.
Iverson, Joseph K.
Fang, Michael T.
Chamberland, Christopher
Painter, Oskar
Brandão, Fernando G. S. L.
author_facet Hann, Connor T.
Noh, Kyungjoo
Putterman, Harald
Matheny, Matthew H.
Iverson, Joseph K.
Fang, Michael T.
Chamberland, Christopher
Painter, Oskar
Brandão, Fernando G. S. L.
contents Dissipative cat qubits are a promising physical platform for quantum computing, since their large noise bias can enable more hardware-efficient quantum error correction. In this work we theoretically study the long-term prospects of a hybrid cat-transmon quantum computing architecture where dissipative cat qubits play the role of data qubits, and error syndromes are measured using ancillary transmon qubits. The cat qubits' noise bias enables more hardware-efficient quantum error correction, and the use of transmons allows for practical, high-fidelity syndrome measurement. While correction of the dominant cat Z errors with a repetition code has recently been demonstrated in experiment, here we show how the architecture can be scaled beyond a repetition code. In particular, we propose a cat-transmon entangling gate that enables the correction of residual cat X errors in a thin rectangular surface code, so that logical error can be arbitrarily suppressed by increasing code distance. We numerically estimate logical memory performance, finding significant overhead reductions in comparison to architectures without biased noise. For example, with current state-of-the-art coherence, physical error rates of $10^{-3}$ and noise biases in the range $10^{3} - 10^{4}$ are achievable. With this level of performance, the qubit overhead required to reach algorithmically-relevant logical error rates with the cat-transmon architecture matches that of an unbiased-noise architecture with physical error rates in the range $10^{-5} - 10^{-4}$.
format Preprint
id arxiv_https___arxiv_org_abs_2410_23363
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Hybrid cat-transmon architecture for scalable, hardware-efficient quantum error correction
Hann, Connor T.
Noh, Kyungjoo
Putterman, Harald
Matheny, Matthew H.
Iverson, Joseph K.
Fang, Michael T.
Chamberland, Christopher
Painter, Oskar
Brandão, Fernando G. S. L.
Quantum Physics
Dissipative cat qubits are a promising physical platform for quantum computing, since their large noise bias can enable more hardware-efficient quantum error correction. In this work we theoretically study the long-term prospects of a hybrid cat-transmon quantum computing architecture where dissipative cat qubits play the role of data qubits, and error syndromes are measured using ancillary transmon qubits. The cat qubits' noise bias enables more hardware-efficient quantum error correction, and the use of transmons allows for practical, high-fidelity syndrome measurement. While correction of the dominant cat Z errors with a repetition code has recently been demonstrated in experiment, here we show how the architecture can be scaled beyond a repetition code. In particular, we propose a cat-transmon entangling gate that enables the correction of residual cat X errors in a thin rectangular surface code, so that logical error can be arbitrarily suppressed by increasing code distance. We numerically estimate logical memory performance, finding significant overhead reductions in comparison to architectures without biased noise. For example, with current state-of-the-art coherence, physical error rates of $10^{-3}$ and noise biases in the range $10^{3} - 10^{4}$ are achievable. With this level of performance, the qubit overhead required to reach algorithmically-relevant logical error rates with the cat-transmon architecture matches that of an unbiased-noise architecture with physical error rates in the range $10^{-5} - 10^{-4}$.
title Hybrid cat-transmon architecture for scalable, hardware-efficient quantum error correction
topic Quantum Physics
url https://arxiv.org/abs/2410.23363