Technical challenges designing a prototype common readout board for LHCb future upgrades

Fuente: arXiv
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Main Author: Langouët, Julien Jiro
Format: Preprint
Published: 2024
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author Langouët, Julien Jiro
author_facet Langouët, Julien Jiro
contents The LHCb Upgrade I introduced a triggerless data acquisition system, crucial for readout across sub-detectors. Upgrade II aims for fivefold throughput enhancement and requires precise clock distribution. The PCIe400 development significantly boosts performance with 400Gbps bandwidth and advanced FPGA capabilities. Key design considerations included thermal dissipation, power distribution, and signal integrity, addressing power consumption exceeding 220 watts. Additionally, advancements in striplines were achieved through improved simulation methods, reducing processing times while optimizing geometry for performance.
format Preprint
id arxiv_https___arxiv_org_abs_2411_01648
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle Technical challenges designing a prototype common readout board for LHCb future upgrades
Langouët, Julien Jiro
Instrumentation and Detectors
High Energy Physics - Experiment
The LHCb Upgrade I introduced a triggerless data acquisition system, crucial for readout across sub-detectors. Upgrade II aims for fivefold throughput enhancement and requires precise clock distribution. The PCIe400 development significantly boosts performance with 400Gbps bandwidth and advanced FPGA capabilities. Key design considerations included thermal dissipation, power distribution, and signal integrity, addressing power consumption exceeding 220 watts. Additionally, advancements in striplines were achieved through improved simulation methods, reducing processing times while optimizing geometry for performance.
title Technical challenges designing a prototype common readout board for LHCb future upgrades
topic Instrumentation and Detectors
High Energy Physics - Experiment
url https://arxiv.org/abs/2411.01648