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CXL-DMSim: A Full-System CXL Disaggregated Memory Simulator With Comprehensive Silicon Validation

Fuente: arXiv

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Bibliographic Details
Main Authors:	Wang, Yanjing, Wu, Lizhou, Hong, Wentao, Ou, Yang, Wang, Zicong, Gao, Sunfeng, Zhang, Jie, Ma, Sheng, Dong, Dezun, Qi, Xingyun, Lai, Mingche, Xiao, Nong
Format:	Preprint
Published:	2024
Subjects:	Emerging Technologies Hardware Architecture
Online Access:	Acceder al recurso
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