Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing
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arXiv
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| Main Authors: | , , , , , , , , , , , , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866910685716283392 |
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| author | He, Chang Xin, Yue Yang, Longfei Wang, Zewei Tang, Zhidong Luo, Xin Chen, Renhe Wang, Zirui Kong, Shuai Wang, Jianli Tang, Jianshi Kang, Xiaoxu Chen, Shoumian Zhao, Yuhang Hu, Shaojian Kou, Xufeng |
| author_facet | He, Chang Xin, Yue Yang, Longfei Wang, Zewei Tang, Zhidong Luo, Xin Chen, Renhe Wang, Zirui Kong, Shuai Wang, Jianli Tang, Jianshi Kang, Xiaoxu Chen, Shoumian Zhao, Yuhang Hu, Shaojian Kou, Xufeng |
| contents | We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage (VTH) shift at low temperatures. The optimized NMOS and PMOS transistors, featured by VTH<0.2V, sub-threshold swing (SS)<30 mV/dec, and on-state current (Ion)>1.2mA/um at 77K, warrant a reliable sub-0.6V operation. Moreover, the enhanced driving strength of Cryo-CMOS inherited from a higher transconductance leads to marked improvements in elevating the ring oscillator frequency by 20%, while reducing the power consumption of the compute-intensive cryogenic IC system by 37% at 77K. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_03099 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing He, Chang Xin, Yue Yang, Longfei Wang, Zewei Tang, Zhidong Luo, Xin Chen, Renhe Wang, Zirui Kong, Shuai Wang, Jianli Tang, Jianshi Kang, Xiaoxu Chen, Shoumian Zhao, Yuhang Hu, Shaojian Kou, Xufeng Systems and Control We report the design-technology co-optimization (DTCO) scheme to develop a 28-nm cryogenic CMOS (Cryo-CMOS) technology for high-performance computing (HPC). The precise adjustment of halo implants manages to compensate the threshold voltage (VTH) shift at low temperatures. The optimized NMOS and PMOS transistors, featured by VTH<0.2V, sub-threshold swing (SS)<30 mV/dec, and on-state current (Ion)>1.2mA/um at 77K, warrant a reliable sub-0.6V operation. Moreover, the enhanced driving strength of Cryo-CMOS inherited from a higher transconductance leads to marked improvements in elevating the ring oscillator frequency by 20%, while reducing the power consumption of the compute-intensive cryogenic IC system by 37% at 77K. |
| title | Optimized Cryo-CMOS Technology with VTH<0.2V and Ion>1.2mA/um for High-Peformance Computing |
| topic | Systems and Control |
| url | https://arxiv.org/abs/2411.03099 |