Hardware for converting floating-point to the microscaling (MX) format
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arXiv
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| Auteurs principaux: | , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866929577252618240 |
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| author | Gorodecky, Danila Sousa, Leonel |
| author_facet | Gorodecky, Danila Sousa, Leonel |
| contents | This paper proposes hardware converters for the microscaling format (MX-format), a reduced representation of floating-point numbers. We present an algorithm and a memory-free hardware model for converting 32 single-precision floating-point numbers to MX-format. The proposed model supports six different types of MX-format: E5M2, E4M3, E3M2, E2M3, E2M1, and INT8. The conversion process consists of three steps: calculating the maximum absolute value among 32 inputs, generating a shared scale, and producing 32 outputs in the selected MX-format type. The hardware converters were implemented in FPGA, and experimental results demonstrate. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_03149 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Hardware for converting floating-point to the microscaling (MX) format Gorodecky, Danila Sousa, Leonel Hardware Architecture This paper proposes hardware converters for the microscaling format (MX-format), a reduced representation of floating-point numbers. We present an algorithm and a memory-free hardware model for converting 32 single-precision floating-point numbers to MX-format. The proposed model supports six different types of MX-format: E5M2, E4M3, E3M2, E2M3, E2M1, and INT8. The conversion process consists of three steps: calculating the maximum absolute value among 32 inputs, generating a shared scale, and producing 32 outputs in the selected MX-format type. The hardware converters were implemented in FPGA, and experimental results demonstrate. |
| title | Hardware for converting floating-point to the microscaling (MX) format |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2411.03149 |