OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offs
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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866916476941762560 |
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| author | Seyedfaraji, Saeed Jager, Severin Shakibhamedan, Salar Aftab, Asad Rehman, Semeen |
| author_facet | Seyedfaraji, Saeed Jager, Severin Shakibhamedan, Salar Aftab, Asad Rehman, Semeen |
| contents | In-SRAM computing promises energy efficiency, but circuit nonlinearities and PVT variations pose major challenges in designing robust accelerators. To address this, we introduce OPTIMA, a modeling framework that aids in analyzing bit-line discharge and power consumption in 6T-SRAM-based accelerators. It provides insights into limiting factors and enables fast design-space exploration of circuit configurations. Leveraging OPTIMA for in-SRAM multiplications exhibits ~100x simulation speed-up while maintaining an RMS modeling error of 0.88mV. Exploration yields an optimized multiplier with 1.05pJ energy consumption per 4-bit operation and classification accuracies of 71.8% (top-1) and 90.4% (top-5) for ImageNet and 92.5% for CIFAR-10 datasets respectively when applied in quantized DNNs. To further support research and development, we made our tool flow available open source at https://github.com/sevjaeg/optima. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_06846 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offs Seyedfaraji, Saeed Jager, Severin Shakibhamedan, Salar Aftab, Asad Rehman, Semeen Hardware Architecture Performance In-SRAM computing promises energy efficiency, but circuit nonlinearities and PVT variations pose major challenges in designing robust accelerators. To address this, we introduce OPTIMA, a modeling framework that aids in analyzing bit-line discharge and power consumption in 6T-SRAM-based accelerators. It provides insights into limiting factors and enables fast design-space exploration of circuit configurations. Leveraging OPTIMA for in-SRAM multiplications exhibits ~100x simulation speed-up while maintaining an RMS modeling error of 0.88mV. Exploration yields an optimized multiplier with 1.05pJ energy consumption per 4-bit operation and classification accuracies of 71.8% (top-1) and 90.4% (top-5) for ImageNet and 92.5% for CIFAR-10 datasets respectively when applied in quantized DNNs. To further support research and development, we made our tool flow available open source at https://github.com/sevjaeg/optima. |
| title | OPTIMA: Design-Space Exploration of Discharge-Based In-SRAM Computing: Quantifying Energy-Accuracy Trade-Offs |
| topic | Hardware Architecture Performance |
| url | https://arxiv.org/abs/2411.06846 |