Web-Based Simulator of Superscalar RISC-V Processors
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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| _version_ | 1866909386223386624 |
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| author | Jaros, Jiri Majer, Michal Horky, Jakub Vavra, Jan |
| author_facet | Jaros, Jiri Majer, Michal Horky, Jakub Vavra, Jan |
| contents | Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_07721 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Web-Based Simulator of Superscalar RISC-V Processors Jaros, Jiri Majer, Michal Horky, Jakub Vavra, Jan Hardware Architecture Mastering computational architectures is essential for developing fast and power-efficient programs. Our advanced simulator empowers both IT students and professionals to grasp the fundamentals of superscalar RISC-V processors, HW/SW co-design and HPC optimization techniques. With customizable processor and memory architecture, full C compiler support, and detailed runtime statistics, this tool offers a comprehensive learning experience. Enjoy the convenience of a modern, web-based GUI to enhance your understanding and skills. |
| title | Web-Based Simulator of Superscalar RISC-V Processors |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2411.07721 |