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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | https://arxiv.org/abs/2411.08199 |
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Table of Contents:
- This paper conducts a comprehensive system-level analysis of mm-Wave full-duplex transceivers, focusing on a receiver employing a four-stage self-interference cancellation (SIC) process. The analysis aims to optimize the noise and linearity performance requirements of each transceiver block, ensuring that the self-interference (SI) signal does not compromise the receiver's error vector magnitude (EVM) for an OFDM 64-QAM signal. Additionally, the necessary SIC for each stage is calculated to establish feasible noise and linearity specifications for a CMOS-based implementation. The resulting specifications are subsequently validated within a MATLAB Simulink environment, confirming the accuracy of the computed requirements for each block.