Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons
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arXiv
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| author | Afentaki, Florentia Duarte, Paula Carolina Lozano Zervakis, Georgios Tahoori, Mehdi B. |
| author_facet | Afentaki, Florentia Duarte, Paula Carolina Lozano Zervakis, Georgios Tahoori, Mehdi B. |
| contents | Printed electronics technology offers a cost-effectiveand fully-customizable solution to computational needs beyondthe capabilities of traditional silicon technologies, offering ad-vantages such as on-demand manufacturing and conformal, low-cost hardware. However, the low-resolution fabrication of printedelectronics, which results in large feature sizes, poses a challengefor integrating complex designs like those of machine learn-ing (ML) classification systems. Current literature optimizes onlythe Multilayer Perceptron (MLP) circuit within the classificationsystem, while the cost of analog-to-digital converters (ADCs)is overlooked. Printed applications frequently require on-sensorprocessing, yet while the digital classifier has been extensivelyoptimized, the analog-to-digital interfacing, specifically the ADCs,dominates the total area and energy consumption. In this work,we target digital printed MLP classifiers and we propose thedesign of customized ADCs per MLP's input which involvesminimizing the distinct represented numbers for each input,simplifying thus the ADC's circuitry. Incorporating this ADCoptimization in the MLP training, enables eliminating ADC levelsand the respective comparators, while still maintaining highclassification accuracy. Our approach achieves 11.2x lower ADCarea for less than 5% accuracy drop across varying MLPs. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_08674 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons Afentaki, Florentia Duarte, Paula Carolina Lozano Zervakis, Georgios Tahoori, Mehdi B. Hardware Architecture Neural and Evolutionary Computing Printed electronics technology offers a cost-effectiveand fully-customizable solution to computational needs beyondthe capabilities of traditional silicon technologies, offering ad-vantages such as on-demand manufacturing and conformal, low-cost hardware. However, the low-resolution fabrication of printedelectronics, which results in large feature sizes, poses a challengefor integrating complex designs like those of machine learn-ing (ML) classification systems. Current literature optimizes onlythe Multilayer Perceptron (MLP) circuit within the classificationsystem, while the cost of analog-to-digital converters (ADCs)is overlooked. Printed applications frequently require on-sensorprocessing, yet while the digital classifier has been extensivelyoptimized, the analog-to-digital interfacing, specifically the ADCs,dominates the total area and energy consumption. In this work,we target digital printed MLP classifiers and we propose thedesign of customized ADCs per MLP's input which involvesminimizing the distinct represented numbers for each input,simplifying thus the ADC's circuitry. Incorporating this ADCoptimization in the MLP training, enables eliminating ADC levelsand the respective comparators, while still maintaining highclassification accuracy. Our approach achieves 11.2x lower ADCarea for less than 5% accuracy drop across varying MLPs. |
| title | Reducing ADC Front-end Costs During Training of On-sensor Printed Multilayer Perceptrons |
| topic | Hardware Architecture Neural and Evolutionary Computing |
| url | https://arxiv.org/abs/2411.08674 |