Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866929594796343296 |
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| author | Hu, Xiangfei Ye, Yuyang Chen, Tinghuan Yan, Hao Yu, Bei |
| author_facet | Hu, Xiangfei Ye, Yuyang Chen, Tinghuan Yan, Hao Yu, Bei |
| contents | With the shrinking technology nodes, timing optimization becomes increasingly challenging. Approximate logic synthesis (ALS) can perform local approximate changes (LACs) on circuits to optimize timing with the cost of slight inaccuracy. However, existing ALS methods that focus solely on critical path depth reduction (depth-driven methods) or area minimization (area-driven methods) are inefficient in achieving optimal timing improvement. %based on double-chase grey wolf optimizer (DCGWO). where we employ a double-chase grey wolf optimizer to explore and apply LACs, simultaneously bringing excellent critical path shortening and area reduction under error constraints. According to experiments on open-source circuits with TSMC 28nm technology, compared to the SOTA method, our framework can generate approximate circuits with greater critical path delay reduction under different error and area constraints. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_10990 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer Hu, Xiangfei Ye, Yuyang Chen, Tinghuan Yan, Hao Yu, Bei Hardware Architecture With the shrinking technology nodes, timing optimization becomes increasingly challenging. Approximate logic synthesis (ALS) can perform local approximate changes (LACs) on circuits to optimize timing with the cost of slight inaccuracy. However, existing ALS methods that focus solely on critical path depth reduction (depth-driven methods) or area minimization (area-driven methods) are inefficient in achieving optimal timing improvement. %based on double-chase grey wolf optimizer (DCGWO). where we employ a double-chase grey wolf optimizer to explore and apply LACs, simultaneously bringing excellent critical path shortening and area reduction under error constraints. According to experiments on open-source circuits with TSMC 28nm technology, compared to the SOTA method, our framework can generate approximate circuits with greater critical path delay reduction under different error and area constraints. |
| title | Timing-driven Approximate Logic Synthesis Based on Double-chase Grey Wolf Optimizer |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2411.10990 |