:: Library Catalog

Imagen de Portada

Guardado en:

Detalles Bibliográficos
Autores principales:	Hu, Xiangfei, Ye, Yuyang, Chen, Tinghuan, Yan, Hao, Yu, Bei
Formato:	Preprint
Publicado:	2024
Materias:	Hardware Architecture
Acceso en línea:	https://arxiv.org/abs/2411.10990
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

Learning-driven Physically-aware Large-scale Circuit Gate Sizing
por: Ye, Yuyang, et al.
Publicado: (2024)

CPPL: A Circuit Prompt Programming Language
por: Yin, Shuo, et al.
Publicado: (2026)

ML-based AIG Timing Prediction to Enhance Logic Optimization
por: Jiang, Wenjing, et al.
Publicado: (2024)

A Systematic Approach for Multi-objective Double-side Clock Tree Synthesis
por: Jiang, Xun, et al.
Publicado: (2025)

E-morphic: Scalable Equality Saturation for Structural Exploration in Logic Synthesis
por: Chen, Chen, et al.
Publicado: (2025)

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
por: Yin, Shuo, et al.
Publicado: (2026)

QUADOL: A Quality-Driven Approximate Logic Synthesis Method Exploiting Dual-Output LUTs for Modern FPGAs
por: Shi, Jian, et al.
Publicado: (2024)

E-Syn: E-Graph Rewriting with Technology-Aware Cost Functions for Logic Synthesis
por: Chen, Chen, et al.
Publicado: (2024)

Conditional Flood Fill Method in Logic Synthesis
por: Yang, Shitian, et al.
Publicado: (2023)

Deep-Learning-Based Pre-Layout Parasitic Capacitance Prediction on SRAM Designs
por: Shen, Shan, et al.
Publicado: (2025)

SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
por: Li, Chengxi, et al.
Publicado: (2025)

Synthesis of Resource-Efficient Superconducting Circuits with Clock-Free Alternating Logic
por: Volk, Jennifer, et al.
Publicado: (2024)

The Survey of Chiplet-based Integrated Architecture: An EDA perspective
por: Chen, Shixin, et al.
Publicado: (2024)

TRAM: Training Approximate Multiplier Structures for Low-Power AI Accelerators
por: Meng, Chang, et al.
Publicado: (2026)

PD-Swap: Prefill-Decode Logic Swapping for End-to-End LLM Inference on Edge FPGAs via Dynamic Partial Reconfiguration
por: Zhang, Yifan, et al.
Publicado: (2025)

A Unified Framework for Mapping and Synthesis of Approximate R-Blocks CGRAs
por: Alexandris, Georgios, et al.
Publicado: (2025)

Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers
por: Xu, Zhihao, et al.
Publicado: (2025)

Aquas: Enhancing Domain Specialization through Holistic Hardware-Software Co-Optimization based on MLIR
por: Zou, Yuyang, et al.
Publicado: (2025)

OpenACM: An Open-Source SRAM-Based Approximate CiM Compiler
por: Zhou, Yiqi, et al.
Publicado: (2026)

RTL Verification for Secure Speculation Using Contract Shadow Logic
por: Tan, Qinhan, et al.
Publicado: (2024)

RePart: Efficient Hypergraph Partitioning with Logic Replication Optimization for Multi-FPGA System
por: Fu, Zizhuo, et al.
Publicado: (2026)

Déjà Vu Packing: Optimizing FPGA Logic Clustering Runtime via Pattern Memoization
por: Liebster, Milo, et al.
Publicado: (2026)

Evaluating Large Language Models for Automatic Register Transfer Logic Generation via High-Level Synthesis
por: Swaroopa, Sneha, et al.
Publicado: (2024)

Logic Encryption: This Time for Real
por: Karn, Rupesh Raj, et al.
Publicado: (2025)

Variability-Aware Approximate Circuit Synthesis via Genetic Optimization
por: Balaskas, Konstantinos, et al.
Publicado: (2023)

Bitwise Logic Using Phase Change Memory Devices Based on the Pinatubo Architecture
por: Aflalo, Noa, et al.
Publicado: (2024)

Real Time FPGA Based Transformers & VLMs for Vision Tasks: SOTA Designs and Optimizations
por: Sali, Safa Mohammed, et al.
Publicado: (2025)

Fast Cross-Operator Optimization of Attention Dataflow
por: Chang, Haodong, et al.
Publicado: (2026)

Interconnect-Aware Logic Resynthesis for Multi-Die FPGAs
por: Wang, Xiaoke, et al.
Publicado: (2026)

Travel Time Based Task Mapping for NoC-Based DNN Accelerator
por: Chen, Yizhi, et al.
Publicado: (2024)

Analytical Heterogeneous Die-to-Die 3D Placement with Macros
por: Zhao, Yuxuan, et al.
Publicado: (2024)

Reconfigurable Digital RRAM Logic Enables In-Situ Pruning and Learning for Edge AI
por: Wang, Songqi, et al.
Publicado: (2025)

NDSEARCH: Accelerating Graph-Traversal-Based Approximate Nearest Neighbor Search through Near Data Processing
por: Wang, Yitu, et al.
Publicado: (2023)

Intelligent OPC Engineer Assistant for Semiconductor Manufacturing
por: Chen, Guojin, et al.
Publicado: (2024)

Evaluation of Run-Time Energy Efficiency using Controlled Approximation in a RISC-V Core
por: Delavari, Arvin, et al.
Publicado: (2024)

LightningSimV2: Faster and Scalable Simulation for High-Level Synthesis via Graph Compilation and Optimization
por: Sarkar, Rishov, et al.
Publicado: (2024)

Hamun: An Approximate Computation Method to Prolong the Lifespan of ReRAM-Based Accelerators
por: Sabri, Mohammad, et al.
Publicado: (2025)

Real Time FPGA Based CNNs for Detection, Classification, and Tracking in Autonomous Systems: State of the Art Designs and Optimizations
por: Sali, Safa Mohammed, et al.
Publicado: (2025)

VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
por: Qi, Haomin, et al.
Publicado: (2025)

Relational Hoare Logic for High-Level Synthesis of Hardware Accelerators
por: Tanaka, Izumi, et al.
Publicado: (2026)