An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors
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arXiv
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| Main Authors: | , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866912123214364672 |
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| author | Su, Zhe Bencsik, Aron Indiveri, Giacomo Bertozzi, Davide |
| author_facet | Su, Zhe Bencsik, Aron Indiveri, Giacomo Bertozzi, Davide |
| contents | Multi-core neuromorphic processors are becoming increasingly significant due to their energy-efficient local computing and scalable modular architecture, particularly for event-based processing applications. However, minimizing the cost of inter-core communication, which accounts for the majority of energy usage, remains a challenging issue. Beyond optimizing circuit design at lower abstraction levels, an efficient multicast addressing scheme is crucial. We propose a hierarchical bit string encoding scheme that largely expands the addressing capability of state-of-the-art symbol-based schemes for the same number of routing bits. When put at work with a real neuromorphic task, this hierarchical bit string encoding achieves a reduction in area cost by approximately 29% and decreases energy consumption by about 50%. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2411_11545 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors Su, Zhe Bencsik, Aron Indiveri, Giacomo Bertozzi, Davide Hardware Architecture Neural and Evolutionary Computing Multi-core neuromorphic processors are becoming increasingly significant due to their energy-efficient local computing and scalable modular architecture, particularly for event-based processing applications. However, minimizing the cost of inter-core communication, which accounts for the majority of energy usage, remains a challenging issue. Beyond optimizing circuit design at lower abstraction levels, an efficient multicast addressing scheme is crucial. We propose a hierarchical bit string encoding scheme that largely expands the addressing capability of state-of-the-art symbol-based schemes for the same number of routing bits. When put at work with a real neuromorphic task, this hierarchical bit string encoding achieves a reduction in area cost by approximately 29% and decreases energy consumption by about 50%. |
| title | An Efficient Multicast Addressing Encoding Scheme for Multi-Core Neuromorphic Processors |
| topic | Hardware Architecture Neural and Evolutionary Computing |
| url | https://arxiv.org/abs/2411.11545 |