Imagen de Portada

Advancing Cloud Computing Capabilities on gem5 by Implementing the RISC-V Hypervisor Extension

Fuente: arXiv

Guardado en:

Detalles Bibliográficos
Autores principales:	Fragkoulis, George-Marios, Karystinos, Nikos, Papadimitriou, George, Gizopoulos, Dimitris
Formato:	Preprint
Publicado:	2024
Materias:	Hardware Architecture
Acceso en línea:	Acceder al recurso
Etiquetas:	Agregar Etiqueta Sin Etiquetas, Sea el primero en etiquetar este registro!

Ejemplares similares

Hypervisor Extension for a RISC-V Processor
por: Gauchola, Jaume, et al.
Publicado: (2024)

Efficient Implementation of RISC-V Vector Permutation Instructions
por: Titopoulos, Vasileios, et al.
Publicado: (2025)

Design, Implementation and Evaluation of the SVNAPOT Extension on a RISC-V Processor
por: Papadopoulos, Nikolaos-Charalampos, et al.
Publicado: (2024)

ARISE: Automating RISC-V Instruction Set Extension
por: Hager-Clukas, Andreas, et al.
Publicado: (2025)

RISC-V V Vector Extension (RVV) with reduced number of vector registers
por: Jacobs, Eino, et al.
Publicado: (2024)

SpikeStream: Accelerating Spiking Neural Network Inference on RISC-V Clusters with Sparse Computation Extensions
por: Manoni, Simone, et al.
Publicado: (2025)

Unlimited Vector Processing for Wireless Baseband Based on RISC-V Extension
por: Jiang, Limin, et al.
Publicado: (2025)

ARCANE: Adaptive RISC-V Cache Architecture for Near-memory Extensions
por: Petrolo, Vincenzo, et al.
Publicado: (2025)

WebRISC-V: A 64-bit RISC-V Pipeline Simulator for Computer Architecture Classes
por: Giorgi, Roberto, et al.
Publicado: (2025)

Toward Reproducible and Standardized Computer Architecture Simulation with gem5
por: Pai, Kunal, et al.
Publicado: (2025)

RISC-V R-Extension: Advancing Efficiency with Rented-Pipeline for Edge DNN Processing
por: Kim, Won Hyeok, et al.
Publicado: (2024)

Late Breaking Results: A RISC-V ISA Extension for Chaining in Scalar Processors
por: Colagrande, Luca, et al.
Publicado: (2025)

A RISC-V SOC for Terahertz IoT Devices: Implementation and design challenges
por: Zhong, Xinchao, et al.
Publicado: (2024)

Register Dispersion: Reducing the Footprint of the Vector Register File in Vector Engines of Low-Cost RISC-V CPUs
por: Titopoulos, Vasileios, et al.
Publicado: (2025)

VMXDOTP: A RISC-V Vector ISA Extension for Efficient Microscaling (MX) Format Acceleration
por: Wipfli, Max, et al.
Publicado: (2026)

Adding MFMA Support to gem5
por: Kurzynski, Marco, et al.
Publicado: (2025)

Hardware vs. Software Implementation of Warp-Level Features in Vortex RISC-V GPU
por: Pu, Huanzhi, et al.
Publicado: (2025)

VEXP: A Low-Cost RISC-V ISA Extension for Accelerated Softmax Computation in Transformers
por: Wang, Run, et al.
Publicado: (2025)

MXDOTP: A RISC-V ISA Extension for Enabling Microscaling (MX) Floating-Point Dot Products
por: İslamoğlu, Gamze, et al.
Publicado: (2025)

Implementing and Optimizing an Open-Source SD-card Host Controller for RISC-V SoCs
por: Vanoni, Axel, et al.
Publicado: (2026)

MARVEL: An End-to-End Framework for Generating Model-Class Aware Custom RISC-V Extensions for Lightweight AI
por: M, Ajay Kumar, et al.
Publicado: (2025)

Scalable and RISC-V Programmable Near-Memory Computing Architectures for Edge Nodes
por: Caon, Michele, et al.
Publicado: (2024)

A Reconfigurable Approximate Computing RISC-V Platform for Fault-Tolerant Applications
por: Delavari, Arvin, et al.
Publicado: (2024)

Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
por: Scheffler, Paul, et al.
Publicado: (2024)

Wildcat: Educational RISC-V Microprocessors
por: Schoeberl, Martin
Publicado: (2025)

Pedagogically Motivated and Composable Open-Source RISC-V Processors for Computer Science Education
por: McDougall, Ian, et al.
Publicado: (2025)

Spatz: Clustering Compact RISC-V-Based Vector Units to Maximize Computing Efficiency
por: Perotti, Matteo, et al.
Publicado: (2023)

Basilisk: Achieving Competitive Performance with Open EDA Tools on an Open-Source Linux-Capable RISC-V SoC
por: Sauter, Phillippe, et al.
Publicado: (2024)

In-Pipeline Integration of Digital In-Memory-Computing into RISC-V Vector Architecture to Accelerate Deep Learning
por: Spagnolo, Tommaso, et al.
Publicado: (2026)

Assessing Tenstorrent's RISC-V MatMul Acceleration Capabilities
por: Cavagna, Hiari Pizzini, et al.
Publicado: (2025)

parti-gem5: gem5's Timing Mode Parallelised
por: Cubero-Cascante, José, et al.
Publicado: (2023)

Understanding Simulated Architecture via gem5 Call-Stack Profiling
por: Söderström, Johan, et al.
Publicado: (2026)

CHAOS: Controlled Hardware fAult injectOr System for gem5
por: Vinciguerra, Elio, et al.
Publicado: (2026)

Web-Based Simulator of Superscalar RISC-V Processors
por: Jaros, Jiri, et al.
Publicado: (2024)

Support Vector Machines Classification on Bendable RISC-V
por: Vergos, Polykarpos, et al.
Publicado: (2025)

Runtime Energy Monitoring for RISC-V Soft-Cores
por: Scionti, Alberto, et al.
Publicado: (2025)

Optimizing Energy Efficiency in Subthreshold RISC-V Cores
por: Djupdal, Asbjørn, et al.
Publicado: (2025)

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V cores
por: Bertaccini, Luca, et al.
Publicado: (2022)

IzhiRISC-V -- a RISC-V-based Processor with Custom ISA Extension for Spiking Neuron Networks Processing with Izhikevich Neurons
por: Szczerek, Wiktor J., et al.
Publicado: (2025)

Verification and Validation (V&V)-in-the-Loop for RISC-V Design: The Holistic Vision of BZL
por: Ahmed, Sajjad, et al.
Publicado: (2026)