Cover Image

Veryl: A New Hardware Description Language as an Altarnative to SystemVerilog

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Hatta, Naoya, Ishitani, Taichi, Shioya, Ryota
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture B.6.3
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

AES-RV: Hardware-Efficient RISC-V Accelerator with Low-Latency AES Instruction Extension for IoT Security
by: Nguyen, Van Tinh, et al.
Published: (2025)

Integrating SystemC-AMS Power Modeling with a RISC-V ISS for Virtual Prototyping of Battery-operated Embedded Devices
by: Hamdi, Mohamed Amine, et al.
Published: (2024)

An Improved Template for Approximate Computing
by: Rezaalipour, Morteza, et al.
Published: (2025)

Bottom-Up Generation of Verilog Designs for Testing EDA Tools
by: Vieira, João Victor Amorim, et al.
Published: (2025)

Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
by: Fu, Weimin, et al.
Published: (2026)

LLM-based Behaviour Driven Development for Hardware Design
by: Drechsler, Rolf, et al.
Published: (2025)

ProtocolLLM: RTL Benchmark for SystemVerilog Generation of Communication Protocols
by: Sheth, Arnav, et al.
Published: (2025)

ChipCraftBrain: Validation-First RTL Generation via Multi-Agent Orchestration
by: Eryilmaz, Cagri
Published: (2026)

Re-thinking Memory-Bound Limitations in CGRAs
by: Liu, Xiangfeng, et al.
Published: (2025)

ALL-MASK: A Reconfigurable Logic Locking Method for Multicore Architecture with Sequential-Instruction-Oriented Key
by: Wang, Jianfeng, et al.
Published: (2022)

Anvil: A General-Purpose Timing-Safe Hardware Description Language
by: Yu, Jason Zhijingcheng, et al.
Published: (2025)

Biological Intuition on Digital Hardware: An RTL Implementation of Poisson-Encoded SNNs for Static Image Classification
by: Das, Debabrata, et al.
Published: (2026)

OpenEye: A Scalable Open-Source Hardware Accelerator for DNNs
by: Lebold, Denis, et al.
Published: (2026)

Revisiting VerilogEval: A Year of Improvements in Large-Language Models for Hardware Code Generation
by: Pinckney, Nathaniel, et al.
Published: (2024)

VerilogCL: A Contrastive Learning Framework for Robust LLM-Based Verilog Generation
by: Tan, Yan, et al.
Published: (2026)

Comprehensive Formal Verification of Observational Correctness for the CHERIoT-Ibex Processor
by: Ploix, Louis-Emile, et al.
Published: (2025)

A flexible framework for early power and timing comparison of time-multiplexed CGRA kernel executions
by: Aspros, Maxime Henri, et al.
Published: (2025)

ECOLogic: Enabling Circular, Obfuscated, and Adaptive Logic via eFPGA-Augmented SoCs
by: Tashdid, Ishraq, et al.
Published: (2025)

Finite-Time Lyapunov Exponent Calculation on FPGA using High-Level Synthesis Tools
by: de Castro, Manuel, et al.
Published: (2024)

LintLLM: An Open-Source Verilog Linting Framework Based on Large Language Models
by: Fang, Zhigang, et al.
Published: (2025)

Non-interfering On-line and In-field SoC Testing
by: Strauch, Tobias
Published: (2024)

Sequence-Based Incremental Concolic Testing of RTL Models
by: Witharana, Hasini, et al.
Published: (2023)

GainSight: A Unified Framework for Data Lifetime Profiling and Heterogeneous Memory Composition
by: Li, Peijing, et al.
Published: (2025)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)

EvoVerilog: Large Langugage Model Assisted Evolution of Verilog Code
by: Guo, Ping, et al.
Published: (2025)

Nonvolatile Charge-Domain Attention with HZO Ferroelectric Capacitors: A Simulation-Based Device-to-System Evaluation
by: Abouagour, Faris
Published: (2026)

Python-based DSL for generating Verilog model of Synchronous Digital Circuits
by: Datar, Mandar, et al.
Published: (2024)

VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
by: Niu, Juxin, et al.
Published: (2025)

Transaction Level Hierarchy Guided and Functional Coverage Driven Deductive Formal Verification
by: Strauch, Tobias
Published: (2025)

A Hardware Accelerator for the Goemans-Williamson Algorithm
by: Herrera-Martí, D. A., et al.
Published: (2025)

FPGA-Accelerated RISC-V ISA Extensions for Efficient Neural Network Inference on Edge Devices
by: Parameshwara, Arya, et al.
Published: (2025)

HEPPO-GAE: Hardware-Efficient Proximal Policy Optimization with Generalized Advantage Estimation
by: Taha, Hazem, et al.
Published: (2025)

Static Communication Analysis for Hardware Design
by: Rosendahl, Mads, et al.
Published: (2025)

Towards LLM-based Generation of Human-Readable Proofs in Polynomial Formal Verification
by: Drechsler, Rolf
Published: (2025)

A Survey on Hardware Accelerators for Large Language Models
by: Kachris, Christoforos
Published: (2024)

EStacker: Explaining Battery-Less IoT System Performance with Energy Stacks
by: Liedtke, Lukas, et al.
Published: (2025)

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)

Trust Nothing: RTOS Security without Run-Time Software TCB (Extended Version)
by: Ackermann, Eric, et al.
Published: (2026)

InterPUF: Distributed Authentication via Physically Unclonable Functions and Multi-party Computation for Reconfigurable Interposers
by: Tashdid, Ishraq, et al.
Published: (2026)

Annotating Slack Directly on Your Verilog: Fine-Grained RTL Timing Evaluation for Early Optimization
by: Fang, Wenji, et al.
Published: (2024)