Schemato -- An LLM for Netlist-to-Schematic Conversion
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arXiv
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| Autori principali: | , , , , , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| _version_ | 1866909633108508672 |
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| author | Matsuo, Ryoga Uhlich, Stefan Venkitaraman, Arun Bonetti, Andrea Hsieh, Chia-Yu Momeni, Ali Mauch, Lukas Capone, Augusto Ohbuchi, Eisaku Servadei, Lorenzo |
| author_facet | Matsuo, Ryoga Uhlich, Stefan Venkitaraman, Arun Bonetti, Andrea Hsieh, Chia-Yu Momeni, Ali Mauch, Lukas Capone, Augusto Ohbuchi, Eisaku Servadei, Lorenzo |
| contents | Machine learning models are advancing circuit design, particularly in analog circuits. They typically generate netlists that lack human interpretability. This is a problem as human designers heavily rely on the interpretability of circuit diagrams or schematics to intuitively understand, troubleshoot, and develop designs. Hence, to integrate domain knowledge effectively, it is crucial to translate ML-generated netlists into interpretable schematics quickly and accurately. We propose Schemato, a large language model (LLM) for netlist-to-schematic conversion. In particular, we consider our approach in converting netlists to .asc files, text-based schematic description used in LTSpice. Experiments on our circuit dataset show that Schemato achieves up to 76% compilation success rate, surpassing 63% scored by the state-of-the-art LLMs. Furthermore, our experiments show that Schemato generates schematics with an average graph edit distance score and mean structural similarity index measure, scaled by the compilation success rate that are 1.8x and 4.3x higher than the best performing LLMs respectively, demonstrating its ability to generate schematics that are more accurately connected and are closer to the reference human design. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_13899 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Schemato -- An LLM for Netlist-to-Schematic Conversion Matsuo, Ryoga Uhlich, Stefan Venkitaraman, Arun Bonetti, Andrea Hsieh, Chia-Yu Momeni, Ali Mauch, Lukas Capone, Augusto Ohbuchi, Eisaku Servadei, Lorenzo Machine Learning Hardware Architecture B.7.2 Machine learning models are advancing circuit design, particularly in analog circuits. They typically generate netlists that lack human interpretability. This is a problem as human designers heavily rely on the interpretability of circuit diagrams or schematics to intuitively understand, troubleshoot, and develop designs. Hence, to integrate domain knowledge effectively, it is crucial to translate ML-generated netlists into interpretable schematics quickly and accurately. We propose Schemato, a large language model (LLM) for netlist-to-schematic conversion. In particular, we consider our approach in converting netlists to .asc files, text-based schematic description used in LTSpice. Experiments on our circuit dataset show that Schemato achieves up to 76% compilation success rate, surpassing 63% scored by the state-of-the-art LLMs. Furthermore, our experiments show that Schemato generates schematics with an average graph edit distance score and mean structural similarity index measure, scaled by the compilation success rate that are 1.8x and 4.3x higher than the best performing LLMs respectively, demonstrating its ability to generate schematics that are more accurately connected and are closer to the reference human design. |
| title | Schemato -- An LLM for Netlist-to-Schematic Conversion |
| topic | Machine Learning Hardware Architecture B.7.2 |
| url | https://arxiv.org/abs/2411.13899 |