Cover Image

Schemato -- An LLM for Netlist-to-Schematic Conversion

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Matsuo, Ryoga, Uhlich, Stefan, Venkitaraman, Arun, Bonetti, Andrea, Hsieh, Chia-Yu, Momeni, Ali, Mauch, Lukas, Capone, Augusto, Ohbuchi, Eisaku, Servadei, Lorenzo
Format:	Preprint
Published:	2024
Subjects:	Machine Learning Hardware Architecture B.7.2
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

GraCo -- A Graph Composer for Integrated Circuits
by: Uhlich, Stefan, et al.
Published: (2024)

SPICEMixer - Netlist-Level Circuit Evolution
by: Uhlich, Stefan, et al.
Published: (2025)

GENIE-ASI: Generative Instruction and Executable Code for Analog Subcircuit Identification
by: Pham, Phuoc, et al.
Published: (2025)

Locality-aware Surrogates for Gradient-based Black-box Optimization
by: Momeni, Ali, et al.
Published: (2025)

Accelerating OTA Circuit Design: Transistor Sizing Based on a Transformer Model and Precomputed Lookup Tables
by: Ghosh, Subhadip, et al.
Published: (2025)

AXON: An Automated Netlist Optimization Framework for High-Speed Adders
by: Yang, Tiantian, et al.
Published: (2026)

HWE-Bench: Can Language Models Perform Board-level Schematic Designs?
by: Qiu, Weibo, et al.
Published: (2026)

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
by: Bhandari, Jitendra, et al.
Published: (2024)

Aligning Netlist to Source Code using SynAlign
by: Garg, Sakshi, et al.
Published: (2025)

There and Back Again: A Netlist's Tale with Much Egraphin'
by: Smith, Gus Henry, et al.
Published: (2024)

DE-HNN: An effective neural model for Circuit Netlist representation
by: Luo, Zhishang, et al.
Published: (2024)

SynFuzz: Leveraging Fuzzing of Netlist to Detect Synthesis Bugs
by: Saravanan, Raghul, et al.
Published: (2025)

ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power Analysis
by: Li, Wenkai, et al.
Published: (2025)

RISCBench: Benchmarking RISC-V Orchestration Efficiency in FPGA and FPGA-Like Computing Engines
by: Ojika, Dave, et al.
Published: (2025)

EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
by: Zhu, Jiaying, et al.
Published: (2026)

ArtNet: Hierarchical Clustering-Based Artificial Netlist Generator for ML and DTCO Application
by: Kang, Andrew B. Kahng. Seokhyeong, et al.
Published: (2025)

GenEDA: Towards Generative Netlist Functional Reasoning via Cross-Modal Circuit Encoder-Decoder Alignment
by: Fang, Wenji, et al.
Published: (2025)

NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed Graph
by: Fang, Wenji, et al.
Published: (2025)

An Integrated UVM-TLM Co-Simulation Framework for RISC-V Functional Verification and Performance Evaluation
by: Qiu, Ruizhi, et al.
Published: (2025)

AiEDA: Agentic AI Design Framework for Digital ASIC System Design
by: Patra, Aditya, et al.
Published: (2024)

Wrong Code, Right Structure: Learning Netlist Representations from Imperfect LLM-Generated RTL
by: Cai, Siyang, et al.
Published: (2026)

Photonic AI: A Hybrid Diffractive Holographic Neural System for Passive Optical Real-Time Image Classification
by: Hiremath, Prakul Sunil
Published: (2026)

Analog Solver Circuit for Linear Symmetric Positive-Definite Systems at a Complexity Independent of Matrix Size
by: Abdelaleim, Osama, et al.
Published: (2025)

RARO: Reliability-aware Conversion with Enhanced Read Performance for QLC SSDs
by: Wang, Yanyun, et al.
Published: (2025)

ArchXBench: A Complex Digital Systems Benchmark Suite for LLM Driven RTL Synthesis
by: Purini, Suresh, et al.
Published: (2025)

Late Breaking Result: FPGA-Based Emulation and Fault Injection for CNN Inference Accelerators
by: Masar, Filip, et al.
Published: (2025)

From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)

SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable Architectures
by: Tirelli, Cristian, et al.
Published: (2025)

An Open-Source Flow for Single-Phase, Edge-Triggered to Two-Phase, Non-Overlapping Clocking Conversion
by: Pedroso, Paolo, et al.
Published: (2026)

Marco: Configurable Graph-Based Task Solving and Multi-AI Agents Framework for Hardware Design
by: Ho, Chia-Tung, et al.
Published: (2025)

FPGA-Optimized Hardware Accelerator for Fast Fourier Transform and Singular Value Decomposition in AI
by: Ding, Hong, et al.
Published: (2025)

NISTT: A Non-Intrusive SystemC-TLM 2.0 Tracing Tool
by: Bosbach, Nils, et al.
Published: (2022)

The Data Conversion Bottleneck in Analog Computing Accelerators
by: Meech, James T., et al.
Published: (2023)

Precomputed 1D-CNNs for Atrial Fibrillation Detection on Tiny Smart Sensor Systems
by: Einhaus, Lukas, et al.
Published: (2026)

TRAPTI: Time-Resolved Analysis for SRAM Banking and Power Gating Optimization in Embedded Transformer Inference
by: Klhufek, Jan, et al.
Published: (2026)

Ara2: Exploring Single- and Multi-Core Vector Processing with an Efficient RVV 1.0 Compliant Open-Source Processor
by: Perotti, Matteo, et al.
Published: (2023)

Analyzing Modern NVIDIA GPU cores
by: Huerta, Rodrigo, et al.
Published: (2025)

Towards Zero-Stall Matrix Multiplication on Energy-Efficient RISC-V Clusters for Machine Learning Acceleration
by: Colagrande, Luca, et al.
Published: (2025)

A "New Ara" for Vector Computing: An Open Source Highly Efficient RISC-V V 1.0 Vector Processor Design
by: Perotti, Matteo, et al.
Published: (2022)

Toward Open-Source Chiplets for HPC and AI: Occamy and Beyond
by: Scheffler, Paul, et al.
Published: (2025)