Saved in:
| Main Authors: | , , , , , , , , , , , , , , , |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | https://arxiv.org/abs/2411.14954 |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1866908818628149248 |
|---|---|
| author | Chaver, D. Harris, S. Pinuel, L. Kindgren, O. Kravitz, R. Gomez, J. I. Castro, F. Olcoz, K. Villalba, J. Grinshpun, A. Gabbay, F. Seed, L. Duarte, R. Lopez, M. Alonso, O. Owen, R. |
| author_facet | Chaver, D. Harris, S. Pinuel, L. Kindgren, O. Kravitz, R. Gomez, J. I. Castro, F. Olcoz, K. Villalba, J. Grinshpun, A. Gabbay, F. Seed, L. Duarte, R. Lopez, M. Alonso, O. Owen, R. |
| contents | The RVfpga course offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and the VeeR EL2, developed by Western Digital a few years ago and currently hosted by ChipsAlliance. This course is particularly aimed at educators and students in computer science, computer engineering, and related fields, enabling them to integrate practical RISC-V knowledge into their curricula. The course materials, which include detailed labs and setup guides, are available for free through the Imagination University Programme website. We have used RVfpga in different teaching activities and we plan to continue using it in the future. Specifically, we have used RVfpga as the main experimental platform in several bachelor/master degree courses; we have completed several final bachelor/master degree projects based on this platform; we will conduct a microcredential about processor design based on RVfpga; we have adapted RVfpga to a MOOC in the edX platform; and we have shared RVfpga worldwide through one-day hands-on workshops and tutorials. This paper begins by discussing how the RVfpga course matches the latest IEEE/ACM/AAAI computing curriculum guidelines. It then details various teaching implementations we have conducted over recent years using these materials. Finally, the paper examines other courses similar to RVfpga, comparing their strengths and weaknesses. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_14954 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Teaching Experiences using the RVfpga Package Chaver, D. Harris, S. Pinuel, L. Kindgren, O. Kravitz, R. Gomez, J. I. Castro, F. Olcoz, K. Villalba, J. Grinshpun, A. Gabbay, F. Seed, L. Duarte, R. Lopez, M. Alonso, O. Owen, R. Hardware Architecture The RVfpga course offers a solid introduction to computer architecture using the RISC-V instruction set and FPGA technology. It focuses on providing hands-on experience with real-world RISC-V cores, the VeeR EH1 and the VeeR EL2, developed by Western Digital a few years ago and currently hosted by ChipsAlliance. This course is particularly aimed at educators and students in computer science, computer engineering, and related fields, enabling them to integrate practical RISC-V knowledge into their curricula. The course materials, which include detailed labs and setup guides, are available for free through the Imagination University Programme website. We have used RVfpga in different teaching activities and we plan to continue using it in the future. Specifically, we have used RVfpga as the main experimental platform in several bachelor/master degree courses; we have completed several final bachelor/master degree projects based on this platform; we will conduct a microcredential about processor design based on RVfpga; we have adapted RVfpga to a MOOC in the edX platform; and we have shared RVfpga worldwide through one-day hands-on workshops and tutorials. This paper begins by discussing how the RVfpga course matches the latest IEEE/ACM/AAAI computing curriculum guidelines. It then details various teaching implementations we have conducted over recent years using these materials. Finally, the paper examines other courses similar to RVfpga, comparing their strengths and weaknesses. |
| title | Teaching Experiences using the RVfpga Package |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2411.14954 |