A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS
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arXiv
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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866915091764477952 |
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| author | Montanaro, Gabriele Galimberti, Andrea Zoni, Davide |
| author_facet | Montanaro, Gabriele Galimberti, Andrea Zoni, Davide |
| contents | Frameworks for the agile development of modern system-on-chips are crucial to dealing with the complexity of designing such architectures. The open-source Vespa framework for designing large, FPGA-based, multi-core heterogeneous system-on-chips enables a faster and more flexible design space exploration of such architectures and their run-time optimization. Vespa, built on ESP, introduces the capabilities to instantiate multiple replicas of the same accelerator in a single network-on-chip node and to partition the system-on-chips into frequency islands with independent dynamic frequency scaling actuators, as well as a dedicated run-time monitoring infrastructure. Experiments on 4-by-4 tile-based system-on-chips demonstrate the possibility of effectively exploring a multitude of solutions that differ in the replication of accelerators, the clock frequencies of the frequency islands, and the tiles' placement, as well as monitoring a variety of statistics related to the traffic on the interconnect and the accelerators' performance at run time. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2411_15574 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS Montanaro, Gabriele Galimberti, Andrea Zoni, Davide Hardware Architecture Frameworks for the agile development of modern system-on-chips are crucial to dealing with the complexity of designing such architectures. The open-source Vespa framework for designing large, FPGA-based, multi-core heterogeneous system-on-chips enables a faster and more flexible design space exploration of such architectures and their run-time optimization. Vespa, built on ESP, introduces the capabilities to instantiate multiple replicas of the same accelerator in a single network-on-chip node and to partition the system-on-chips into frequency islands with independent dynamic frequency scaling actuators, as well as a dedicated run-time monitoring infrastructure. Experiments on 4-by-4 tile-based system-on-chips demonstrate the possibility of effectively exploring a multitude of solutions that differ in the replication of accelerators, the clock frequencies of the frequency islands, and the tiles' placement, as well as monitoring a variety of statistics related to the traffic on the interconnect and the accelerators' performance at run time. |
| title | A Prototype-Based Framework to Design Scalable Heterogeneous SoCs with Fine-Grained DFS |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2411.15574 |