Anda: Unlocking Efficient LLM Inference with a Variable-Length Grouped Activation Data Format
Fuente:
arXiv
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| Main Authors: | Fang, Chao, Shi, Man, Geens, Robin, Symons, Arne, Wang, Zhongfeng, Verhelst, Marian |
|---|---|
| Format: | Preprint |
| Published: |
2024
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| Subjects: | |
| Online Access: | |
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