UVLLM: An Automated Universal RTL Verification Framework using LLMs
Fuente:
arXiv
Saved in:
| Main Authors: | Hu, Yuchen, Ye, Junhao, Xu, Ke, Sun, Jialin, Zhang, Shiyue, Jiao, Xinyao, Pan, Dingrong, Zhou, Jie, Wang, Ning, Shan, Weiwei, Fang, Xinwei, Wang, Xi, Guan, Nan, Jiang, Zhe |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)
by: Ye, Junhao, et al.
Published: (2026)
MEIC: Re-thinking RTL Debug Automation using LLMs
by: Xu, Ke, et al.
Published: (2024)
by: Xu, Ke, et al.
Published: (2024)
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
by: Ye, Junhao, et al.
Published: (2025)
by: Ye, Junhao, et al.
Published: (2025)
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
by: Zhou, Jie, et al.
Published: (2025)
by: Zhou, Jie, et al.
Published: (2025)
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
by: Sun, Jialin, et al.
Published: (2025)
by: Sun, Jialin, et al.
Published: (2025)
Insights from Verification: Training a Verilog Generation LLM with Reinforcement Learning with Testbench Feedback
by: Wang, Ning, et al.
Published: (2025)
by: Wang, Ning, et al.
Published: (2025)
Think with Self-Decoupling and Self-Verification: Automated RTL Design with Backtrack-ToT
by: Chao, Zhiteng, et al.
Published: (2025)
by: Chao, Zhiteng, et al.
Published: (2025)
Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)
by: Orenes-Vera, Marcelo, et al.
Published: (2023)
ChatModel: Automating Reference Model Design and Verification with LLMs
by: Ye, Jianmin, et al.
Published: (2025)
by: Ye, Jianmin, et al.
Published: (2025)
VerilogMonkey: Exploring Parallel Scaling for Automated Verilog Code Generation with LLMs
by: Niu, Juxin, et al.
Published: (2025)
by: Niu, Juxin, et al.
Published: (2025)
ACE-RTL: When Agentic Context Evolution Meets RTL-Specialized LLMs
by: Deng, Chenhui, et al.
Published: (2026)
by: Deng, Chenhui, et al.
Published: (2026)
RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)
by: Tan, Qinhan, et al.
Published: (2024)
ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
by: Deng, Chenhui, et al.
Published: (2025)
by: Deng, Chenhui, et al.
Published: (2025)
FERIVer: An FPGA-assisted Emulated Framework for RTL Verification of RISC-V Processors
by: Qin, Kun, et al.
Published: (2025)
by: Qin, Kun, et al.
Published: (2025)
From Indiscriminate to Targeted: Efficient RTL Verification via Functionally Key Signal-Driven LLM Assertion Generation
by: Wang, Yonghao, et al.
Published: (2026)
by: Wang, Yonghao, et al.
Published: (2026)
Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning
by: Wang, Ning, et al.
Published: (2024)
by: Wang, Ning, et al.
Published: (2024)
Automated SVA Generation with LLMs
by: Fu, Lik Tung, et al.
Published: (2026)
by: Fu, Lik Tung, et al.
Published: (2026)
VeriDebug: A Unified LLM for Verilog Debugging via Contrastive Embedding and Guided Correction
by: Wang, Ning, et al.
Published: (2025)
by: Wang, Ning, et al.
Published: (2025)
VeriRAG: A Retrieval-Augmented Framework for Automated RTL Testability Repair
by: Qi, Haomin, et al.
Published: (2025)
by: Qi, Haomin, et al.
Published: (2025)
ChatSVA: Bridging SVA Generation for Hardware Verification via Task-Specific LLMs
by: Fu, Lik Tung, et al.
Published: (2026)
by: Fu, Lik Tung, et al.
Published: (2026)
Location is Key: Leveraging Large Language Model for Functional Bug Localization in Verilog
by: Yao, Bingkun, et al.
Published: (2024)
by: Yao, Bingkun, et al.
Published: (2024)
FIXME: Towards End-to-End Benchmarking of LLM-Aided Design Verification
by: Wan, Gwok-Waa, et al.
Published: (2025)
by: Wan, Gwok-Waa, et al.
Published: (2025)
PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)
by: Yin, Shuo, et al.
Published: (2026)
RTL-Repo: A Benchmark for Evaluating LLMs on Large-Scale RTL Design Projects
by: Allam, Ahmed, et al.
Published: (2024)
by: Allam, Ahmed, et al.
Published: (2024)
OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)
by: Liu, Shang, et al.
Published: (2025)
From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)
by: Krupp, Lukas, et al.
Published: (2026)
Automated Multi-Agent Workflows for RTL Design
by: Bhattaram, Amulya, et al.
Published: (2025)
by: Bhattaram, Amulya, et al.
Published: (2025)
HAVEN: Hybrid Automated Verification ENgine for UVM Testbench Synthesis with LLMs
by: Meng, Chang-Chih, et al.
Published: (2026)
by: Meng, Chang-Chih, et al.
Published: (2026)
LAAG-RV: LLM Assisted Assertion Generation for RTL Design Verification
by: Maddala, Karthik, et al.
Published: (2024)
by: Maddala, Karthik, et al.
Published: (2024)
SmaRTLy: RTL Optimization with Logic Inferencing and Structural Rebuilding
by: Li, Chengxi, et al.
Published: (2025)
by: Li, Chengxi, et al.
Published: (2025)
SpecLoop: An Agentic RTL-to-Specification Framework with Formal Verification Feedback Loop
by: Chang, Fu-Chieh, et al.
Published: (2026)
by: Chang, Fu-Chieh, et al.
Published: (2026)
PRO-V-R1: Reasoning Enhanced Programming Agent for RTL Verification
by: Zhao, Yujie, et al.
Published: (2025)
by: Zhao, Yujie, et al.
Published: (2025)
Spec2RTL-Agent: Automated Hardware Code Generation from Complex Specifications Using LLM Agent Systems
by: Yu, Zhongzhi, et al.
Published: (2025)
by: Yu, Zhongzhi, et al.
Published: (2025)
FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)
by: Li, Kezhi, et al.
Published: (2026)
ERASER: Efficient RTL FAult Simulation Framework with Trimmed Execution Redundancy
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
ReChisel: Effective Automatic Chisel Code Generation by LLM with Reflection
by: Niu, Juxin, et al.
Published: (2025)
by: Niu, Juxin, et al.
Published: (2025)
Hot-LEGO: Architect Microfluidic Cooling Equipped 3DICs with Pre-RTL Thermal Simulation
by: Wang, Runxi, et al.
Published: (2024)
by: Wang, Runxi, et al.
Published: (2024)
Dr. RTL: Autonomous Agentic RTL Optimization through Tool-Grounded Self-Improvement
by: Fang, Wenji, et al.
Published: (2026)
by: Fang, Wenji, et al.
Published: (2026)
Extend IVerilog to Support Batch RTL Fault Simulation
by: Tang, Jiaping, et al.
Published: (2025)
by: Tang, Jiaping, et al.
Published: (2025)
GSIM: Accelerating RTL Simulation for Large-Scale Designs
by: Chen, Lu, et al.
Published: (2025)
by: Chen, Lu, et al.
Published: (2025)
Similar Items
-
UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026) -
MEIC: Re-thinking RTL Debug Automation using LLMs
by: Xu, Ke, et al.
Published: (2024) -
From Concept to Practice: an Automated LLM-aided UVM Machine for RTL Verification
by: Ye, Junhao, et al.
Published: (2025) -
Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL Design
by: Zhou, Jie, et al.
Published: (2025) -
ISAAC: Intelligent, Scalable, Agile, and Accelerated CPU Verification via LLM-aided FPGA Parallelism
by: Sun, Jialin, et al.
Published: (2025)