Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment

Ähnliche Einträge

• A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
  von: Torrens, Gabriel, et al.
  Veröffentlicht: (2024)
• A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement
  von: Gomi, Yuibi, et al.
  Veröffentlicht: (2025)
• An Affordable Experimental Technique for SRAM Write Margin Characterization for Nanometer CMOS Technologies
  von: Alorda, Bartomeu, et al.
  Veröffentlicht: (2024)
• SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results
  von: Torrens, Gabriel, et al.
  Veröffentlicht: (2024)
• Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout
  von: Gonski, Julia, et al.
  Veröffentlicht: (2024)