Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment
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arXiv
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| Auteurs principaux: | , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866929605715165184 |
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| author | Malagon, Daniel Torrens, Gabriel Segura, Jaume Bota, Sebastia A. |
| author_facet | Malagon, Daniel Torrens, Gabriel Segura, Jaume Bota, Sebastia A. |
| contents | We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistors (6T) and eight-transistors (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of the CERN High-energy Accelerator test facility (CHARM) at the European Organization for Nuclear Research in Geneva, Switzerland. A 1.45x higher SEU cross-section was observed for 6T-cell designs despite the larger area occupied by the 8T cells (1.5x for MCU). Moreover, the trend for events affecting multiple bits was higher in 6T-cells. The cross-section obtained values show that the memories have enough sensitivity to be used as a radiation monitors in high energy physics experiments. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2411_17198 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment Malagon, Daniel Torrens, Gabriel Segura, Jaume Bota, Sebastia A. Instrumentation and Detectors Hardware Architecture High Energy Physics - Experiment We present experimental results of the cross-section related to cosmic-ray irradiation at ground level for minimum-sized six-transistors (6T) and eight-transistors (8T) bit-cells SRAM memories implemented on a 65 nm CMOS standard technology. Results were obtained from accelerated irradiation tests performed in the mixed-field irradiation facility of the CERN High-energy Accelerator test facility (CHARM) at the European Organization for Nuclear Research in Geneva, Switzerland. A 1.45x higher SEU cross-section was observed for 6T-cell designs despite the larger area occupied by the 8T cells (1.5x for MCU). Moreover, the trend for events affecting multiple bits was higher in 6T-cells. The cross-section obtained values show that the memories have enough sensitivity to be used as a radiation monitors in high energy physics experiments. |
| title | Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment |
| topic | Instrumentation and Detectors Hardware Architecture High Energy Physics - Experiment |
| url | https://arxiv.org/abs/2411.17198 |