Single Event Upsets characterization of 65 nm CMOS 6T and 8T SRAM cells for ground level environment
Fuente:
arXiv
Saved in:
| Main Authors: | Malagon, Daniel, Torrens, Gabriel, Segura, Jaume, Bota, Sebastia A. |
|---|---|
| Format: | Preprint |
| Published: |
2024
|
| Subjects: | |
| Online Access: | |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
Similar Items
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
by: Torrens, Gabriel, et al.
Published: (2024)
by: Torrens, Gabriel, et al.
Published: (2024)
A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement
by: Gomi, Yuibi, et al.
Published: (2025)
by: Gomi, Yuibi, et al.
Published: (2025)
An Affordable Experimental Technique for SRAM Write Margin Characterization for Nanometer CMOS Technologies
by: Alorda, Bartomeu, et al.
Published: (2024)
by: Alorda, Bartomeu, et al.
Published: (2024)
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results
by: Torrens, Gabriel, et al.
Published: (2024)
by: Torrens, Gabriel, et al.
Published: (2024)
Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout
by: Gonski, Julia, et al.
Published: (2024)
by: Gonski, Julia, et al.
Published: (2024)
Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis
by: Devadze, Sergei, et al.
Published: (2024)
by: Devadze, Sergei, et al.
Published: (2024)
Delay Time Characterization on FPGA: A Low Nonlinearity, Picosecond Resolution Time-to-Digital Converter on 16-nm FPGA using Bin Sequence Calibration
by: Park, Sunwoo, et al.
Published: (2025)
by: Park, Sunwoo, et al.
Published: (2025)
Analyzing the Single Event Upset Vulnerability of Binarized Neural Networks on SRAM FPGAs
by: Souvatzoglou, Ioanna, et al.
Published: (2024)
by: Souvatzoglou, Ioanna, et al.
Published: (2024)
Trikarenos: Design and Experimental Characterization of a Fault-Tolerant 28nm RISC-V-based SoC
by: Rogenmoser, Michael, et al.
Published: (2024)
by: Rogenmoser, Michael, et al.
Published: (2024)
LL-GNN: Low Latency Graph Neural Networks on FPGAs for High Energy Physics
by: Que, Zhiqiang, et al.
Published: (2022)
by: Que, Zhiqiang, et al.
Published: (2022)
HEEPidermis: a versatile SoC for BioZ recording
by: Sapriza, Juan, et al.
Published: (2025)
by: Sapriza, Juan, et al.
Published: (2025)
VERTECS: A COTS-based payload interface board to enable next generation astronomical imaging payloads
by: Fielding, Ezra, et al.
Published: (2024)
by: Fielding, Ezra, et al.
Published: (2024)
wa-hls4ml: A Benchmark and Surrogate Models for hls4ml Resource and Latency Estimation
by: Hawks, Benjamin, et al.
Published: (2025)
by: Hawks, Benjamin, et al.
Published: (2025)
Low latency optical-based mode tracking with machine learning deployed on FPGAs on a tokamak
by: Wei, Yumou, et al.
Published: (2023)
by: Wei, Yumou, et al.
Published: (2023)
Hardware acceleration for ultra-fast Neural Network training on FPGA for MRF map reconstruction
by: Ricchi, Mattia, et al.
Published: (2025)
by: Ricchi, Mattia, et al.
Published: (2025)
Using Formal Verification to Evaluate Single Event Upsets in a RISC-V Core
by: Xue, Bing, et al.
Published: (2024)
by: Xue, Bing, et al.
Published: (2024)
Analysis of Hardware Synthesis Strategies for Machine Learning in Collider Trigger and Data Acquisition
by: Jia, Haoyi, et al.
Published: (2024)
by: Jia, Haoyi, et al.
Published: (2024)
Bias Variation Compensation in Perimeter-Gated SPAD TRNGs
by: Sajal, Md Sakibur, et al.
Published: (2025)
by: Sajal, Md Sakibur, et al.
Published: (2025)
Machine Learning on Heterogeneous, Edge, and Quantum Hardware for Particle Physics (ML-HEQUPP)
by: Gonski, Julia, et al.
Published: (2026)
by: Gonski, Julia, et al.
Published: (2026)
Single-Event Upset Analysis of a Systolic Array based Deep Neural Network Accelerator
by: Jonckers, Naïn, et al.
Published: (2024)
by: Jonckers, Naïn, et al.
Published: (2024)
A 33.6-136.2 TOPS/W Nonlinear Analog Computing-In-Memory Macro for Multi-bit LSTM Accelerator in 65 nm CMOS
by: Yang, Junyi, et al.
Published: (2025)
by: Yang, Junyi, et al.
Published: (2025)
A 65nm 8b-Activation 8b-Weight SRAM-Based Charge-Domain Computing-in-Memory Macro Using A Fully-Parallel Analog Adder Network and A Single-ADC Interface
by: Yin, Guodong, et al.
Published: (2022)
by: Yin, Guodong, et al.
Published: (2022)
Ultra8T: A Sub-Threshold 8T SRAM with Leakage Detection
by: Shen, Shan, et al.
Published: (2023)
by: Shen, Shan, et al.
Published: (2023)
Simulations and Performance Studies of a MAPS in 65 nm CMOS Imaging Technology
by: Simancas, Adriana, et al.
Published: (2024)
by: Simancas, Adriana, et al.
Published: (2024)
SRAM-PG: Power Delivery Network Benchmarks from SRAM Circuits
by: Shen, Shan, et al.
Published: (2024)
by: Shen, Shan, et al.
Published: (2024)
The H2M Monolithic Active Pixel Sensor -- characterizing non-uniform in-pixel response in a 65 nm CMOS imaging technology
by: Daza, Sara Ruiz, et al.
Published: (2025)
by: Daza, Sara Ruiz, et al.
Published: (2025)
Further Characterisation of Digital Pixel Test Structures Implemented in a 65 nm CMOS Process
by: Rinella, Gianluca Aglieri, et al.
Published: (2025)
by: Rinella, Gianluca Aglieri, et al.
Published: (2025)
CIMple: Standard-cell SRAM-based CIM with LUT-based split softmax for attention acceleration
by: Ahn, Bas, et al.
Published: (2026)
by: Ahn, Bas, et al.
Published: (2026)
Basilisk: An End-to-End Open-Source Linux-Capable RISC-V SoC in 130nm CMOS
by: Scheffler, Paul, et al.
Published: (2024)
by: Scheffler, Paul, et al.
Published: (2024)
Characterisation of analogue Monolithic Active Pixel Sensor test structures implemented in a 65 nm CMOS imaging process
by: Rinella, Gianluca Aglieri, et al.
Published: (2024)
by: Rinella, Gianluca Aglieri, et al.
Published: (2024)
Time performance of Analog Pixel Test Structures with in-chip operational amplifier implemented in 65 nm CMOS imaging process
by: Rinella, Gianluca Aglieri, et al.
Published: (2024)
by: Rinella, Gianluca Aglieri, et al.
Published: (2024)
A Review of SRAM-based Compute-in-Memory Circuits
by: Yoshioka, Kentaro, et al.
Published: (2024)
by: Yoshioka, Kentaro, et al.
Published: (2024)
Developing a Monolithic Silicon Sensor in a 65 nm CMOS Imaging Technology for Future Lepton Collider Vertex Detectors
by: Simancas, Adriana, et al.
Published: (2023)
by: Simancas, Adriana, et al.
Published: (2023)
A 28nm 1.80Mb/mm2 Digital/Analog Hybrid SRAM-CIM Macro Using 2D-Weighted Capacitor Array for Complex Number Mac Operations
by: Konno, Shota, et al.
Published: (2025)
by: Konno, Shota, et al.
Published: (2025)
CryptoSRAM: Enabling High-Throughput Cryptography on MCUs via In-SRAM Computing
by: Zhang, Jingyao, et al.
Published: (2025)
by: Zhang, Jingyao, et al.
Published: (2025)
AccelCIM: Systematic Dataflow Exploration for SRAM Compute-in-Memory Accelerator
by: Xue, Chenhao, et al.
Published: (2026)
by: Xue, Chenhao, et al.
Published: (2026)
Electrical Impedance Tomography with an Integrated Picoliter-Volume Subtractive Microfluidic Chamber in 65 nm CMOS
by: de Oliveira, Antonio Victor Machado, et al.
Published: (2025)
by: de Oliveira, Antonio Victor Machado, et al.
Published: (2025)
ModSRAM: Algorithm-Hardware Co-Design for Large Number Modular Multiplication in SRAM
by: Ku, Jonathan, et al.
Published: (2024)
by: Ku, Jonathan, et al.
Published: (2024)
Dose rate dependence of TID damage to 65 nm CMOS transistors in X-ray irradiations of the ATLAS ITk Pixel ASIC (ITkPix)
by: Bortoletto, Daniela, et al.
Published: (2024)
by: Bortoletto, Daniela, et al.
Published: (2024)
OpenACM: An Open-Source SRAM-Based Approximate CiM Compiler
by: Zhou, Yiqi, et al.
Published: (2026)
by: Zhou, Yiqi, et al.
Published: (2026)
Similar Items
-
A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors
by: Torrens, Gabriel, et al.
Published: (2024) -
A 55-nm SRAM Chip Scanning Errors Every 125 ns for Event-Wise Soft Error Measurement
by: Gomi, Yuibi, et al.
Published: (2025) -
An Affordable Experimental Technique for SRAM Write Margin Characterization for Nanometer CMOS Technologies
by: Alorda, Bartomeu, et al.
Published: (2024) -
SRAM Alpha-SER Estimation From Word-Line Voltage Margin Measurements: Design Architecture and Experimental Results
by: Torrens, Gabriel, et al.
Published: (2024) -
Embedded FPGA Developments in 130nm and 28nm CMOS for Machine Learning in Particle Detector Readout
by: Gonski, Julia, et al.
Published: (2024)