RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation

Fuente: arXiv
Salvato in:
Dettagli Bibliografici
Autori principali: Mankali, Lakshmi Likhitha, Bhandari, Jitendra, Alam, Manaar, Karri, Ramesh, Maniatakos, Michail, Sinanoglu, Ozgur, Knechtel, Johann
Natura: Preprint
Pubblicazione: 2024
Soggetti:
Accesso online:
Tags: Aggiungi Tag
Nessun Tag, puoi essere il primo ad aggiungerne!!
_version_ 1866910743720361984
author Mankali, Lakshmi Likhitha
Bhandari, Jitendra
Alam, Manaar
Karri, Ramesh
Maniatakos, Michail
Sinanoglu, Ozgur
Knechtel, Johann
author_facet Mankali, Lakshmi Likhitha
Bhandari, Jitendra
Alam, Manaar
Karri, Ramesh
Maniatakos, Michail
Sinanoglu, Ozgur
Knechtel, Johann
contents Large language models (LLMs) have demonstrated remarkable potential with code generation/completion tasks for hardware design. In fact, LLM-based hardware description language (HDL) code generation has enabled the industry to realize complex designs more quickly, reducing the time and effort required in the development cycle. However, the increased reliance on such automation introduces critical security risks. Notably, given that LLMs have to be trained on vast datasets of codes that are typically sourced from publicly available repositories (often without thorough validation), LLMs are susceptible to so-called data poisoning or backdoor attacks. Here, attackers inject malicious code for the training data, which can be carried over into the HDL code generated by LLMs. This threat vector can compromise the security and integrity of entire hardware systems. In this work, we propose RTL-Breaker, a novel backdoor attack framework on LLM-based HDL code generation. RTL-Breaker provides an in-depth analysis for essential aspects of this novel problem: 1) various trigger mechanisms versus their effectiveness for inserting malicious modifications, and 2) side-effects by backdoor attacks on code generation in general, i.e., impact on code quality. RTL-Breaker emphasizes the urgent need for more robust measures to safeguard against such attacks. Toward that end, we open-source our framework and all data.
format Preprint
id arxiv_https___arxiv_org_abs_2411_17569
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
Mankali, Lakshmi Likhitha
Bhandari, Jitendra
Alam, Manaar
Karri, Ramesh
Maniatakos, Michail
Sinanoglu, Ozgur
Knechtel, Johann
Cryptography and Security
Hardware Architecture
Large language models (LLMs) have demonstrated remarkable potential with code generation/completion tasks for hardware design. In fact, LLM-based hardware description language (HDL) code generation has enabled the industry to realize complex designs more quickly, reducing the time and effort required in the development cycle. However, the increased reliance on such automation introduces critical security risks. Notably, given that LLMs have to be trained on vast datasets of codes that are typically sourced from publicly available repositories (often without thorough validation), LLMs are susceptible to so-called data poisoning or backdoor attacks. Here, attackers inject malicious code for the training data, which can be carried over into the HDL code generated by LLMs. This threat vector can compromise the security and integrity of entire hardware systems. In this work, we propose RTL-Breaker, a novel backdoor attack framework on LLM-based HDL code generation. RTL-Breaker provides an in-depth analysis for essential aspects of this novel problem: 1) various trigger mechanisms versus their effectiveness for inserting malicious modifications, and 2) side-effects by backdoor attacks on code generation in general, i.e., impact on code quality. RTL-Breaker emphasizes the urgent need for more robust measures to safeguard against such attacks. Toward that end, we open-source our framework and all data.
title RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation
topic Cryptography and Security
Hardware Architecture
url https://arxiv.org/abs/2411.17569