Cover Image

RTL-Breaker: Assessing the Security of LLMs against Backdoor Attacks on HDL Code Generation

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Mankali, Lakshmi Likhitha, Bhandari, Jitendra, Alam, Manaar, Karri, Ramesh, Maniatakos, Michail, Sinanoglu, Ozgur, Knechtel, Johann
Format:	Preprint
Published:	2024
Subjects:	Cryptography and Security Hardware Architecture
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

VeriContaminated: Assessing LLM-Driven Verilog Coding for Data Contamination
by: Wang, Zeng, et al.
Published: (2025)

Veritas: Deterministic Verilog Code Synthesis from LLM-Generated Conjunctive Normal Form
by: Roy, Prithwish Basu, et al.
Published: (2025)

LLMs and the Future of Chip Design: Unveiling Security Risks and Building Trust
by: Wang, Zeng, et al.
Published: (2024)

LLMs for Secure Hardware Design and Related Problems: Opportunities and Challenges
by: Knechtel, Johann, et al.
Published: (2026)

VeriLeaky: Navigating IP Protection vs Utility in Fine-Tuning for LLM-Driven Verilog Coding
by: Wang, Zeng, et al.
Published: (2025)

Lightweight Countermeasures Against Static Power Side-Channel Attacks
by: Bhandari, Jitendra, et al.
Published: (2024)

LLM-Aided Testbench Generation and Bug Detection for Finite-State Machines
by: Bhandari, Jitendra, et al.
Published: (2024)

Logic Encryption: This Time for Real
by: Karn, Rupesh Raj, et al.
Published: (2025)

Configuration Over Selection: Hyperparameter Sensitivity Exceeds Model Differences in Open-Source LLMs for RTL Generation
by: Shao, Minghao, et al.
Published: (2026)

Synthesis-in-the-Loop Evaluation of LLMs for RTL Generation: Quality, Reliability, and Failure Modes
by: Fu, Weimin, et al.
Published: (2026)

TrojanGYM: A Detector-in-the-Loop LLM for Adaptive RTL Hardware Trojan Insertion
by: Sreekumar, Saideep, et al.
Published: (2026)

From Natural Language to Silicon: The Representation Bottleneck in LLM Hardware Design
by: Fu, Weimin, et al.
Published: (2026)

VeriLoC: Line-of-Code Level Prediction of Hardware Design Quality from Verilog Code
by: Hemadri, Raghu Vamshi, et al.
Published: (2025)

SALAD: Systematic Assessment of Machine Unlearning on LLM-Aided Hardware Design
by: Wang, Zeng, et al.
Published: (2025)

VeriCWEty: Embedding enabled Line-Level CWE Detection in Verilog
by: Roy, Prithwish Basu, et al.
Published: (2026)

Targeted Wearout Attacks in Microprocessor Cores
by: Mashburn, Joshua, et al.
Published: (2025)

ReVeil: Unconstrained Concealed Backdoor Attack on Deep Neural Networks using Machine Unlearning
by: Alam, Manaar, et al.
Published: (2025)

SENTAUR: Security EnhaNced Trojan Assessment Using LLMs Against Undesirable Revisions
by: Bhandari, Jitendra, et al.
Published: (2024)

TroLLoc: Logic Locking and Layout Hardening for IC Security Closure against Hardware Trojans
by: Wang, Fangzhou, et al.
Published: (2024)

Masala-CHAI: A Large-Scale SPICE Netlist Dataset for Analog Circuits by Harnessing AI
by: Bhandari, Jitendra, et al.
Published: (2024)

@NTT: Algorithm-Targeted NTT hardware acceleration via Design-Time Constant Optimization
by: Nabeel, Mohammed, et al.
Published: (2026)

Large Language Models (LLMs) for Electronic Design Automation (EDA)
by: Xu, Kangwei, et al.
Published: (2025)

ASCENT: Amplifying Power Side-Channel Resilience via Learning & Monte-Carlo Tree Search
by: Bhandari, Jitendra, et al.
Published: (2024)

CoFHEE: A Co-processor for Fully Homomorphic Encryption Execution (Extended Version)
by: Nabeel, Mohammed, et al.
Published: (2022)

Make Every Move Count: LLM-based High-Quality RTL Code Generation Using MCTS
by: DeLorenzo, Matthew, et al.
Published: (2024)

DRAUN: An Algorithm-Agnostic Data Reconstruction Attack on Federated Unlearning Systems
by: Lamri, Hithem, et al.
Published: (2025)

C2HLSC: Can LLMs Bridge the Software-to-Hardware Design Gap?
by: Collini, Luca, et al.
Published: (2024)

LockForge: Automating Paper-to-Code for Logic Locking with Multi-Agent Reasoning LLMs
by: Saha, Akashdeep, et al.
Published: (2025)

RTL Verification for Secure Speculation Using Contract Shadow Logic
by: Tan, Qinhan, et al.
Published: (2024)

RTL++: Graph-enhanced LLM for RTL Code Generation
by: Akyash, Mohammad, et al.
Published: (2025)

TrojanLoC: LLM-based Framework for RTL Trojan Localization
by: Xiao, Weihua, et al.
Published: (2025)

VeriInteresting: An Empirical Study of Model Prompt Interactions in Verilog Code Generation
by: Collini, Luca, et al.
Published: (2026)

NetDeTox: Adversarial and Efficient Evasion of Hardware-Security GNNs via RL-LLM Orchestration
by: Wang, Zeng, et al.
Published: (2025)

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)

ScaleRTL: Scaling LLMs with Reasoning Data and Test-Time Compute for Accurate RTL Code Generation
by: Deng, Chenhui, et al.
Published: (2025)

Assessing Large Language Models in Generating RTL Design Specifications
by: Huang, Hung-Ming, et al.
Published: (2025)

PipeRTL: Timing-Aware Pipeline Optimization at IR-Level for RTL Generation
by: Yin, Shuo, et al.
Published: (2026)

From RTL to Prompt Coding: Empowering the Next Generation of Chip Designers through LLMs
by: Krupp, Lukas, et al.
Published: (2026)

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design RTL Generation
by: Liu, Shang, et al.
Published: (2025)

Classification-Based Automatic HDL Code Generation Using LLMs
by: Sun, Wenhao, et al.
Published: (2024)