High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms

Fuente: arXiv
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Main Authors: Wang, Hao, Xiao, Erjia, Mu, Wenbo, He, Songhuan, Ni, Zhongyi, Zhang, Lingfeng, Zhan, Xiaokun, Cui, Yifei, Liu, Jinguo, Wang, Cheng, Wang, Zhongrui, Xu, Renjing
Format: Preprint
Published: 2024
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author Wang, Hao
Xiao, Erjia
Mu, Wenbo
He, Songhuan
Ni, Zhongyi
Zhang, Lingfeng
Zhan, Xiaokun
Cui, Yifei
Liu, Jinguo
Wang, Cheng
Wang, Zhongrui
Xu, Renjing
author_facet Wang, Hao
Xiao, Erjia
Mu, Wenbo
He, Songhuan
Ni, Zhongyi
Zhang, Lingfeng
Zhan, Xiaokun
Cui, Yifei
Liu, Jinguo
Wang, Cheng
Wang, Zhongrui
Xu, Renjing
contents Due to the high sensitivity of qubits to environmental noise, which leads to decoherence and information loss, active quantum error correction(QEC) is essential. Surface codes represent one of the most promising fault-tolerant QEC schemes, but they require decoders that are accurate, fast, and scalable to large-scale quantum platforms. In all types of decoders, fully neural network-based high-level decoders offer decoding thresholds that surpass baseline decoder-Minimum Weight Perfect Matching (MWPM), and exhibit strong scalability, making them one of the ideal solutions for addressing surface code challenges. However, current fully neural network-based high-level decoders can only operate serially and do not meet the current latency requirements (below 440 ns). To address these challenges, we first propose a parallel fully feedforward neural network (FFNN) high-level surface code decoder, and comprehensively measure its decoding performance on a computing-in-memory (CIM) hardware simulation platform. With the currently available hardware specifications, our work achieves a decoding threshold of 14.22%, surpassing the MWPM baseline of 10.3%, and achieves high pseudo-thresholds of 10.4%, 11.3%, 12%, and 11.6% with decoding latencies of 197.03 ns, 234.87 ns, 243.73 ns, and 251.65 ns for distances of 3, 5, 7 and 9, respectively. The impact of hardware parameters and non-idealities on these results is discussed, and the hardware simulation results are extrapolated to a 4K quantum cryogenic environment.
format Preprint
id arxiv_https___arxiv_org_abs_2411_18090
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms
Wang, Hao
Xiao, Erjia
Mu, Wenbo
He, Songhuan
Ni, Zhongyi
Zhang, Lingfeng
Zhan, Xiaokun
Cui, Yifei
Liu, Jinguo
Wang, Cheng
Wang, Zhongrui
Xu, Renjing
Hardware Architecture
Due to the high sensitivity of qubits to environmental noise, which leads to decoherence and information loss, active quantum error correction(QEC) is essential. Surface codes represent one of the most promising fault-tolerant QEC schemes, but they require decoders that are accurate, fast, and scalable to large-scale quantum platforms. In all types of decoders, fully neural network-based high-level decoders offer decoding thresholds that surpass baseline decoder-Minimum Weight Perfect Matching (MWPM), and exhibit strong scalability, making them one of the ideal solutions for addressing surface code challenges. However, current fully neural network-based high-level decoders can only operate serially and do not meet the current latency requirements (below 440 ns). To address these challenges, we first propose a parallel fully feedforward neural network (FFNN) high-level surface code decoder, and comprehensively measure its decoding performance on a computing-in-memory (CIM) hardware simulation platform. With the currently available hardware specifications, our work achieves a decoding threshold of 14.22%, surpassing the MWPM baseline of 10.3%, and achieves high pseudo-thresholds of 10.4%, 11.3%, 12%, and 11.6% with decoding latencies of 197.03 ns, 234.87 ns, 243.73 ns, and 251.65 ns for distances of 3, 5, 7 and 9, respectively. The impact of hardware parameters and non-idealities on these results is discussed, and the hardware simulation results are extrapolated to a 4K quantum cryogenic environment.
title High-Level Surface Code Decoding via Parallel FFNNs on CIM Platforms
topic Hardware Architecture
url https://arxiv.org/abs/2411.18090