A 65-nm Reliable 6T CMOS SRAM Cell with Minimum Size Transistors

Fuente: arXiv

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Bibliographic Details
Main Authors:	Torrens, Gabriel, Alorda, Bartomeu, Carmona, Cristian, Malagon-Perianez, Daniel, Segura, Jaume, Bota, Sebastia Antoni
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2411.18114