Instruction Scheduling in the Saturn Vector Unit
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arXiv
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| Hauptverfasser: | , , , , , , |
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| Format: | Preprint |
| Veröffentlicht: |
2024
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| _version_ | 1866929610148544512 |
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| author | Zhao, Jerry Grubb, Daniel Rusch, Miles Wei, Tianrui Anderson, Kevin Nikolic, Borivoje Asanovic, Krste |
| author_facet | Zhao, Jerry Grubb, Daniel Rusch, Miles Wei, Tianrui Anderson, Kevin Nikolic, Borivoje Asanovic, Krste |
| contents | While the challenges and solutions for efficient execution of scalable vector ISAs on long-vector-length microarchitectures have been well established, not all of these solutions are suitable for short-vector-length implementations. This work proposes a novel microarchitecture for instruction sequencing in vector units with short architectural vector lengths. The proposed microarchitecture supports fine-granularity chaining, multi-issue out-of-order execution, zero dead-time, and run-ahead memory accesses with low area or complexity costs. We present the Saturn Vector Unit, a RTL implementation of a RVV vector unit. With our instruction scheduling mechanism, Saturn exhibits comparable or superior power, performance, and area characteristics compared to state-of-the-art long-vector and short-vector implementations. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2412_00997 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Instruction Scheduling in the Saturn Vector Unit Zhao, Jerry Grubb, Daniel Rusch, Miles Wei, Tianrui Anderson, Kevin Nikolic, Borivoje Asanovic, Krste Hardware Architecture While the challenges and solutions for efficient execution of scalable vector ISAs on long-vector-length microarchitectures have been well established, not all of these solutions are suitable for short-vector-length implementations. This work proposes a novel microarchitecture for instruction sequencing in vector units with short architectural vector lengths. The proposed microarchitecture supports fine-granularity chaining, multi-issue out-of-order execution, zero dead-time, and run-ahead memory accesses with low area or complexity costs. We present the Saturn Vector Unit, a RTL implementation of a RVV vector unit. With our instruction scheduling mechanism, Saturn exhibits comparable or superior power, performance, and area characteristics compared to state-of-the-art long-vector and short-vector implementations. |
| title | Instruction Scheduling in the Saturn Vector Unit |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2412.00997 |