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| Main Authors: | , |
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| Format: | Preprint |
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2024
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| Online Access: | https://arxiv.org/abs/2412.01764 |
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| _version_ | 1866916503160356864 |
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| author | Balasubramanian, Padmanabhan Maskell, Douglas L. |
| author_facet | Balasubramanian, Padmanabhan Maskell, Douglas L. |
| contents | We present a novel fast bipartitioned hybrid adder (FBHA) that utilizes carry-select and carry-lookahead logic. The proposed FBHA is an accurate adder with a significant part and a less significant part joined together by a carry signal. In an N-bit FBHA, the K-bit less significant part is realized using carry-lookahead adder logic, and the (N-K)-bit significant part is realized using carry-select adder logic. The 32-bit addition was considered as an example operation for this work. Many 32-bit adders ranging from the slow ripple carry adder to the fast parallel-prefix Kogge-Stone adder and the proposed adder were synthesized using a 28-nm CMOS standard cell library and their design metrics were compared. A well-optimized FBHA achieved significant optimizations in design metrics compared to its high-speed adder counterparts and some examples are mentioned as follows: (a) 19.8% reduction in delay compared to a carry-lookahead adder; (b) 19.8% reduction in delay, 24.4% reduction in area, and 19.4% reduction in power compared to a carry-select adder; (c) 45.6% reduction in delay, and 13.5% reduction in power compared to a conditional sum adder; and (d) 46.5% reduction in area, and 29.3% reduction in power compared to the Kogge-Stone adder. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2412_01764 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic Balasubramanian, Padmanabhan Maskell, Douglas L. Hardware Architecture We present a novel fast bipartitioned hybrid adder (FBHA) that utilizes carry-select and carry-lookahead logic. The proposed FBHA is an accurate adder with a significant part and a less significant part joined together by a carry signal. In an N-bit FBHA, the K-bit less significant part is realized using carry-lookahead adder logic, and the (N-K)-bit significant part is realized using carry-select adder logic. The 32-bit addition was considered as an example operation for this work. Many 32-bit adders ranging from the slow ripple carry adder to the fast parallel-prefix Kogge-Stone adder and the proposed adder were synthesized using a 28-nm CMOS standard cell library and their design metrics were compared. A well-optimized FBHA achieved significant optimizations in design metrics compared to its high-speed adder counterparts and some examples are mentioned as follows: (a) 19.8% reduction in delay compared to a carry-lookahead adder; (b) 19.8% reduction in delay, 24.4% reduction in area, and 19.4% reduction in power compared to a carry-select adder; (c) 45.6% reduction in delay, and 13.5% reduction in power compared to a conditional sum adder; and (d) 46.5% reduction in area, and 29.3% reduction in power compared to the Kogge-Stone adder. |
| title | Fast Bipartitioned Hybrid Adder Utilizing Carry Select and Carry Lookahead Logic |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2412.01764 |