Hard Math -- Easy UVM: Pragmatic solutions for verifying hardware algorithms using UVM
Fuente:
arXiv
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| Autori principali: | , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| Soggetti: | |
| Accesso online: | |
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| _version_ | 1866910764120408064 |
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| author | Litterick, Mark Ivankovic, Aleksandar Arsov, Bojan Kumar, Aman |
| author_facet | Litterick, Mark Ivankovic, Aleksandar Arsov, Bojan Kumar, Aman |
| contents | This paper presents pragmatic solutions for verifying complex mathematical algorithms implemented in hardware in an efficient and effective manner. Maximizing leverage of a known-answer-test strategy, based on predefined data scenarios combined with design-for-verification modes, we demonstrate how to find and isolate concept and design bugs early in the flow. The solutions presented are based on real project experience with single chip radar sensors for a variety of applications. The verification environments supporting the presented strategies are based on SystemVerilog and the Universal Verification Methodology. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2412_04919 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | Hard Math -- Easy UVM: Pragmatic solutions for verifying hardware algorithms using UVM Litterick, Mark Ivankovic, Aleksandar Arsov, Bojan Kumar, Aman Artificial Intelligence Hardware Architecture Logic in Computer Science This paper presents pragmatic solutions for verifying complex mathematical algorithms implemented in hardware in an efficient and effective manner. Maximizing leverage of a known-answer-test strategy, based on predefined data scenarios combined with design-for-verification modes, we demonstrate how to find and isolate concept and design bugs early in the flow. The solutions presented are based on real project experience with single chip radar sensors for a variety of applications. The verification environments supporting the presented strategies are based on SystemVerilog and the Universal Verification Methodology. |
| title | Hard Math -- Easy UVM: Pragmatic solutions for verifying hardware algorithms using UVM |
| topic | Artificial Intelligence Hardware Architecture Logic in Computer Science |
| url | https://arxiv.org/abs/2412.04919 |