DocEDA: Automated Extraction and Design of Analog Circuits from Documents with Large Language Model
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arXiv
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| Main Authors: | , , , , , |
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| Format: | Preprint |
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2024
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| _version_ | 1866916512484294656 |
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| author | Chen, Hong Cai Wu, Longchang Gao, Ming Shen, Lingrui Zhong, Jiarui Xu, Yipin |
| author_facet | Chen, Hong Cai Wu, Longchang Gao, Ming Shen, Lingrui Zhong, Jiarui Xu, Yipin |
| contents | Efficient and accurate extraction of electrical parameters from circuit datasheets and design documents is critical for accelerating circuit design in Electronic Design Automation (EDA). Traditional workflows often rely on engineers manually searching and extracting these parameters, which is time-consuming, and prone to human error. To address these challenges, we introduce DocEDA, an automated system that leverages advanced computer vision techniques and Large Language Models (LLMs) to extract electrical parameters seamlessly from documents. The layout analysis model specifically designed for datasheet is proposed to classify documents into circuit-related parts. Utilizing the inherent Chain-of-Thought reasoning capabilities of LLMs, DocEDA automates the extraction of electronic component parameters from documents. For circuit diagrams parsing, an improved GAM-YOLO model is hybrid with topology identification to transform diagrams into circuit netlists. Then, a space mapping enhanced optimization framework is evoked for optimization the layout in the document. Experimental evaluations demonstrate that DocEDA significantly enhances the efficiency of processing circuit design documents and the accuracy of electrical parameter extraction. It exhibits adaptability to various circuit design scenarios and document formats, offering a novel solution for EDA with the potential to transform traditional methodologies. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2412_05301 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | DocEDA: Automated Extraction and Design of Analog Circuits from Documents with Large Language Model Chen, Hong Cai Wu, Longchang Gao, Ming Shen, Lingrui Zhong, Jiarui Xu, Yipin Hardware Architecture Artificial Intelligence Computation and Language Efficient and accurate extraction of electrical parameters from circuit datasheets and design documents is critical for accelerating circuit design in Electronic Design Automation (EDA). Traditional workflows often rely on engineers manually searching and extracting these parameters, which is time-consuming, and prone to human error. To address these challenges, we introduce DocEDA, an automated system that leverages advanced computer vision techniques and Large Language Models (LLMs) to extract electrical parameters seamlessly from documents. The layout analysis model specifically designed for datasheet is proposed to classify documents into circuit-related parts. Utilizing the inherent Chain-of-Thought reasoning capabilities of LLMs, DocEDA automates the extraction of electronic component parameters from documents. For circuit diagrams parsing, an improved GAM-YOLO model is hybrid with topology identification to transform diagrams into circuit netlists. Then, a space mapping enhanced optimization framework is evoked for optimization the layout in the document. Experimental evaluations demonstrate that DocEDA significantly enhances the efficiency of processing circuit design documents and the accuracy of electrical parameter extraction. It exhibits adaptability to various circuit design scenarios and document formats, offering a novel solution for EDA with the potential to transform traditional methodologies. |
| title | DocEDA: Automated Extraction and Design of Analog Circuits from Documents with Large Language Model |
| topic | Hardware Architecture Artificial Intelligence Computation and Language |
| url | https://arxiv.org/abs/2412.05301 |