A High Energy-Efficiency Multi-core Neuromorphic Architecture for Deep SNN Training

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Hauptverfasser: Li, Mingjing, Zhou, Huihui, Xu, Xiaofeng, Zhong, Zhiwei, Quan, Puli, Zhu, Xueke, Lin, Yanyu, Lin, Wenjie, Guo, Hongyu, Zhang, Junchao, Ma, Yunhao, Wang, Wei, Meng, Qingyan, Ma, Zhengyu, Li, Guoqi, Cui, Xiaoxin, Tian, Yonghong
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Veröffentlicht: 2024
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author Li, Mingjing
Zhou, Huihui
Xu, Xiaofeng
Zhong, Zhiwei
Quan, Puli
Zhu, Xueke
Lin, Yanyu
Lin, Wenjie
Guo, Hongyu
Zhang, Junchao
Ma, Yunhao
Wang, Wei
Meng, Qingyan
Ma, Zhengyu
Li, Guoqi
Cui, Xiaoxin
Tian, Yonghong
author_facet Li, Mingjing
Zhou, Huihui
Xu, Xiaofeng
Zhong, Zhiwei
Quan, Puli
Zhu, Xueke
Lin, Yanyu
Lin, Wenjie
Guo, Hongyu
Zhang, Junchao
Ma, Yunhao
Wang, Wei
Meng, Qingyan
Ma, Zhengyu
Li, Guoqi
Cui, Xiaoxin
Tian, Yonghong
contents There is a growing necessity for edge training to adapt to dynamically changing environment. Neuromorphic computing represents a significant pathway for high-efficiency intelligent computation in energy-constrained edges, but existing neuromorphic architectures lack the ability of directly training spiking neural networks (SNNs) based on backpropagation. We develop a multi-core neuromorphic architecture with Feedforward-Propagation, Back-Propagation, and Weight-Gradient engines in each core, supporting high efficient parallel computing at both the engine and core levels. It combines various data flows and sparse computation optimization by fully leveraging the sparsity in SNN training, obtaining a high energy efficiency of 1.05TFLOPS/W@ FP16 @ 28nm, 55 ~ 85% reduction of DRAM access compared to A100 GPU in SNN trainings, and a 20-core deep SNN training and a 5-worker federated learning on FPGAs. Our study develops the first multi-core neuromorphic architecture supporting the direct SNN training, facilitating the neuromorphic computing in edge-learnable applications.
format Preprint
id arxiv_https___arxiv_org_abs_2412_05302
institution arXiv
publishDate 2024
record_format arxiv
spellingShingle A High Energy-Efficiency Multi-core Neuromorphic Architecture for Deep SNN Training
Li, Mingjing
Zhou, Huihui
Xu, Xiaofeng
Zhong, Zhiwei
Quan, Puli
Zhu, Xueke
Lin, Yanyu
Lin, Wenjie
Guo, Hongyu
Zhang, Junchao
Ma, Yunhao
Wang, Wei
Meng, Qingyan
Ma, Zhengyu
Li, Guoqi
Cui, Xiaoxin
Tian, Yonghong
Hardware Architecture
Distributed, Parallel, and Cluster Computing
Machine Learning
There is a growing necessity for edge training to adapt to dynamically changing environment. Neuromorphic computing represents a significant pathway for high-efficiency intelligent computation in energy-constrained edges, but existing neuromorphic architectures lack the ability of directly training spiking neural networks (SNNs) based on backpropagation. We develop a multi-core neuromorphic architecture with Feedforward-Propagation, Back-Propagation, and Weight-Gradient engines in each core, supporting high efficient parallel computing at both the engine and core levels. It combines various data flows and sparse computation optimization by fully leveraging the sparsity in SNN training, obtaining a high energy efficiency of 1.05TFLOPS/W@ FP16 @ 28nm, 55 ~ 85% reduction of DRAM access compared to A100 GPU in SNN trainings, and a 20-core deep SNN training and a 5-worker federated learning on FPGAs. Our study develops the first multi-core neuromorphic architecture supporting the direct SNN training, facilitating the neuromorphic computing in edge-learnable applications.
title A High Energy-Efficiency Multi-core Neuromorphic Architecture for Deep SNN Training
topic Hardware Architecture
Distributed, Parallel, and Cluster Computing
Machine Learning
url https://arxiv.org/abs/2412.05302