DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent
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arXiv
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| Main Authors: | , , , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866909419064786944 |
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| author | Chang, Chen-Chia Ho, Chia-Tung Li, Yaguang Chen, Yiran Ren, Haoxing |
| author_facet | Chang, Chen-Chia Ho, Chia-Tung Li, Yaguang Chen, Yiran Ren, Haoxing |
| contents | In the advanced technology nodes, the integrated design rule checker (DRC) is often utilized in place and route tools for fast optimization loops for power-performance-area. Implementing integrated DRC checkers to meet the standard of commercial DRC tools demands extensive human expertise to interpret foundry specifications, analyze layouts, and debug code iteratively. However, this labor-intensive process, requiring to be repeated by every update of technology nodes, prolongs the turnaround time of designing circuits. In this paper, we present DRC-Coder, a multi-agent framework with vision capabilities for automated DRC code generation. By incorporating vision language models and large language models (LLM), DRC-Coder can effectively process textual, visual, and layout information to perform rule interpretation and coding by two specialized LLMs. We also design an auto-evaluation function for LLMs to enable DRC code debugging. Experimental results show that targeting on a sub-3nm technology node for a state-of-the-art standard cell layout tool, DRC-Coder achieves perfect F1 score 1.000 in generating DRC codes for meeting the standard of a commercial DRC tool, highly outperforming standard prompting techniques (F1=0.631). DRC-Coder can generate code for each design rule within four minutes on average, which significantly accelerates technology advancement and reduces engineering costs. |
| format | Preprint |
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arxiv_https___arxiv_org_abs_2412_05311 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent Chang, Chen-Chia Ho, Chia-Tung Li, Yaguang Chen, Yiran Ren, Haoxing Hardware Architecture Artificial Intelligence In the advanced technology nodes, the integrated design rule checker (DRC) is often utilized in place and route tools for fast optimization loops for power-performance-area. Implementing integrated DRC checkers to meet the standard of commercial DRC tools demands extensive human expertise to interpret foundry specifications, analyze layouts, and debug code iteratively. However, this labor-intensive process, requiring to be repeated by every update of technology nodes, prolongs the turnaround time of designing circuits. In this paper, we present DRC-Coder, a multi-agent framework with vision capabilities for automated DRC code generation. By incorporating vision language models and large language models (LLM), DRC-Coder can effectively process textual, visual, and layout information to perform rule interpretation and coding by two specialized LLMs. We also design an auto-evaluation function for LLMs to enable DRC code debugging. Experimental results show that targeting on a sub-3nm technology node for a state-of-the-art standard cell layout tool, DRC-Coder achieves perfect F1 score 1.000 in generating DRC codes for meeting the standard of a commercial DRC tool, highly outperforming standard prompting techniques (F1=0.631). DRC-Coder can generate code for each design rule within four minutes on average, which significantly accelerates technology advancement and reduces engineering costs. |
| title | DRC-Coder: Automated DRC Checker Code Generation Using LLM Autonomous Agent |
| topic | Hardware Architecture Artificial Intelligence |
| url | https://arxiv.org/abs/2412.05311 |