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| Autori principali: | , , , , , |
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| Natura: | Preprint |
| Pubblicazione: |
2024
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| Soggetti: | |
| Accesso online: | https://arxiv.org/abs/2412.05323 |
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| _version_ | 1866915052637913088 |
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| author | Taraporewalla, Jehan KP, Arun Ghosh, Sugata Agarwal, Abhishek Basak, Bijaydoot Saha, Dipankar |
| author_facet | Taraporewalla, Jehan KP, Arun Ghosh, Sugata Agarwal, Abhishek Basak, Bijaydoot Saha, Dipankar |
| contents | In application-specific designs, owing to the trade-off between power consumption and speed, optimization of various circuit parameters has become a challenging task. Several of the performance metrics, viz. energy efficiency, gain, performance, and noise immunity, are interrelated and difficult to tune. Such efforts may result in a great deal of manual iterations which in turn increase the computational overhead. Thus, it is important to develop a methodology that not only explores large design space but also reduces the computational time. In this work, we investigate the viability of using a SPICE and Python IDE (PIDE) interface to optimize integrated circuits. The SPICE simulations are carried out using 22 nm technology node with a nominal supply voltage of 0.8 V. The SPICE-PIDE optimizer, as delineated in this work, is able to provide the best solution sets considering various performance metrics and design complexities for 5 transistor level converters. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2412_05323 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | SPICE-PIDE: A Methodology for Design and Optimization of Integrated Circuits Taraporewalla, Jehan KP, Arun Ghosh, Sugata Agarwal, Abhishek Basak, Bijaydoot Saha, Dipankar Other Computer Science Hardware Architecture In application-specific designs, owing to the trade-off between power consumption and speed, optimization of various circuit parameters has become a challenging task. Several of the performance metrics, viz. energy efficiency, gain, performance, and noise immunity, are interrelated and difficult to tune. Such efforts may result in a great deal of manual iterations which in turn increase the computational overhead. Thus, it is important to develop a methodology that not only explores large design space but also reduces the computational time. In this work, we investigate the viability of using a SPICE and Python IDE (PIDE) interface to optimize integrated circuits. The SPICE simulations are carried out using 22 nm technology node with a nominal supply voltage of 0.8 V. The SPICE-PIDE optimizer, as delineated in this work, is able to provide the best solution sets considering various performance metrics and design complexities for 5 transistor level converters. |
| title | SPICE-PIDE: A Methodology for Design and Optimization of Integrated Circuits |
| topic | Other Computer Science Hardware Architecture |
| url | https://arxiv.org/abs/2412.05323 |