HiVeGen -- Hierarchical LLM-based Verilog Generation for Scalable Chip Design

Fuente: arXiv

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Bibliographic Details
Main Authors:	Tang, Jinwei, Qin, Jiayin, Thorat, Kiran, Zhu-Tian, Chen, Cao, Yu, Yang, Zhao, Ding, Caiwen
Format:	Preprint
Published:	2024
Subjects:	Machine Learning Artificial Intelligence Hardware Architecture
Online Access:	Acceder al recurso
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Internet

https://arxiv.org/abs/2412.05393