AiEDA: Agentic AI Design Framework for Digital ASIC System Design
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arXiv
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| Main Authors: | , , |
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| Format: | Preprint |
| Published: |
2024
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| _version_ | 1866917867625119744 |
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| author | Patra, Aditya Rout, Saroj Ravindran, Arun |
| author_facet | Patra, Aditya Rout, Saroj Ravindran, Arun |
| contents | The paper addresses advancements in Generative Artificial Intelligence (GenAI) and digital chip design, highlighting the integration of Large Language Models (LLMs) in automating hardware description and design. LLMs, known for generating human-like content, are now being explored for creating hardware description languages (HDLs) like Verilog from natural language inputs. This approach aims to enhance productivity and reduce costs in VLSI system design. The study introduces "AiEDA", a proposed agentic design flow framework for digital ASIC systems, leveraging autonomous AI agents to manage complex design tasks. AiEDA is designed to streamline the transition from conceptual design to GDSII layout using an open-source toolchain. The framework is demonstrated through the design of an ultra-low-power digital ASIC for KeyWord Spotting (KWS). The use of agentic AI workflows promises to improve design efficiency by automating the integration of multiple design tools, thereby accelerating the development process and addressing the complexities of hardware design. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2412_09745 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | AiEDA: Agentic AI Design Framework for Digital ASIC System Design Patra, Aditya Rout, Saroj Ravindran, Arun Hardware Architecture The paper addresses advancements in Generative Artificial Intelligence (GenAI) and digital chip design, highlighting the integration of Large Language Models (LLMs) in automating hardware description and design. LLMs, known for generating human-like content, are now being explored for creating hardware description languages (HDLs) like Verilog from natural language inputs. This approach aims to enhance productivity and reduce costs in VLSI system design. The study introduces "AiEDA", a proposed agentic design flow framework for digital ASIC systems, leveraging autonomous AI agents to manage complex design tasks. AiEDA is designed to streamline the transition from conceptual design to GDSII layout using an open-source toolchain. The framework is demonstrated through the design of an ultra-low-power digital ASIC for KeyWord Spotting (KWS). The use of agentic AI workflows promises to improve design efficiency by automating the integration of multiple design tools, thereby accelerating the development process and addressing the complexities of hardware design. |
| title | AiEDA: Agentic AI Design Framework for Digital ASIC System Design |
| topic | Hardware Architecture |
| url | https://arxiv.org/abs/2412.09745 |