USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks
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arXiv
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| Auteurs principaux: | , , |
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| Format: | Preprint |
| Publié: |
2024
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| _version_ | 1866908361176383488 |
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| author | Ibrahim, Muhammad Sohail Usman, Muhammad Lee, Jeong-A |
| author_facet | Ibrahim, Muhammad Sohail Usman, Muhammad Lee, Jeong-A |
| contents | Convolutional Neural Networks (CNNs) are crucial in various applications, but their deployment on resource-constrained edge devices poses challenges. This study presents the Sum-of-Products (SOP) units for convolution, which utilize low-latency left-to-right bit-serial arithmetic to minimize response time and enhance overall performance. The study proposes a methodology for fusing multiple convolution layers to reduce off-chip memory communication and increase overall performance. An effective mechanism detects and skips inefficient convolutions after ReLU layers, minimizing power consumption without compromising accuracy. Furthermore, efficient tile movement guarantees uniform access to the fusion pyramid. An analysis demonstrates the utile stride strategy improves operational intensity. Two designs cater to varied demands: one focuses on minimal response time for mission-critical applications, and another focuses on resource-constrained devices with comparable latency. This approach notably reduced redundant computations, improving the efficiency of CNN deployment on edge devices. |
| format | Preprint |
| id |
arxiv_https___arxiv_org_abs_2412_13724 |
| institution | arXiv |
| publishDate | 2024 |
| record_format | arxiv |
| spellingShingle | USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks Ibrahim, Muhammad Sohail Usman, Muhammad Lee, Jeong-A Machine Learning Hardware Architecture Performance Convolutional Neural Networks (CNNs) are crucial in various applications, but their deployment on resource-constrained edge devices poses challenges. This study presents the Sum-of-Products (SOP) units for convolution, which utilize low-latency left-to-right bit-serial arithmetic to minimize response time and enhance overall performance. The study proposes a methodology for fusing multiple convolution layers to reduce off-chip memory communication and increase overall performance. An effective mechanism detects and skips inefficient convolutions after ReLU layers, minimizing power consumption without compromising accuracy. Furthermore, efficient tile movement guarantees uniform access to the fusion pyramid. An analysis demonstrates the utile stride strategy improves operational intensity. Two designs cater to varied demands: one focuses on minimal response time for mission-critical applications, and another focuses on resource-constrained devices with comparable latency. This approach notably reduced redundant computations, improving the efficiency of CNN deployment on edge devices. |
| title | USEFUSE: Uniform Stride for Enhanced Performance in Fused Layer Architecture of Deep Neural Networks |
| topic | Machine Learning Hardware Architecture Performance |
| url | https://arxiv.org/abs/2412.13724 |