ReducedLUT: Table Decomposition with "Don't Care" Conditions

Documenti analoghi

• PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference
  di: Andronic, Marta, et al.
  Pubblicazione: (2023)
• NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions
  di: Andronic, Marta, et al.
  Pubblicazione: (2024)
• PolyLUT: Ultra-low Latency Polynomial Inference with Hardware-Aware Structured Pruning
  di: Andronic, Marta, et al.
  Pubblicazione: (2025)
• BitMoD: Bit-serial Mixture-of-Datatype LLM Acceleration
  di: Chen, Yuzong, et al.
  Pubblicazione: (2024)
• ROVER: RTL Optimization via Verified E-Graph Rewriting
  di: Coward, Samuel, et al.
  Pubblicazione: (2024)