A 64-Channel Precision Time-to-Digital Converter with Average 4.77 ps RMS Implemented in a 28 nm FPGA
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arXiv
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| Auteurs principaux: | Liang, Zehong, Yan, Xiongbo, Ning, Zhe, Hu, Jun, Jiang, Xiaoshan, Sun, Yunhua, Pan, Weiyan, Ye, Jingbo |
|---|---|
| Format: | Preprint |
| Publié: |
2024
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