Cover Image

AnalogXpert: Automating Analog Topology Synthesis by Incorporating Circuit Design Expertise into Large Language Models

Fuente: arXiv

Saved in:

Bibliographic Details
Main Authors:	Zhang, Haoyi, Sun, Shizhao, Lin, Yibo, Wang, Runsheng, Bian, Jiang
Format:	Preprint
Published:	2024
Subjects:	Hardware Architecture Artificial Intelligence Software Engineering
Online Access:	Acceder al recurso
Tags:	Add Tag No Tags, Be the first to tag this record!

Similar Items

AutoINV: Automated Invariant Generation Framework for Formal Verification on High-Level Synthesis Designs
by: Zhou, Xiaofeng, et al.
Published: (2026)

C2HLSC: Leveraging Large Language Models to Bridge the Software-to-Hardware Design Gap
by: Collini, Luca, et al.
Published: (2024)

MEIC: Re-thinking RTL Debug Automation using LLMs
by: Xu, Ke, et al.
Published: (2024)

LayoutCopilot: An LLM-powered Multi-agent Collaborative Framework for Interactive Analog Layout Design
by: Liu, Bingyang, et al.
Published: (2024)

EasyACIM: An End-to-End Automated Analog CIM with Synthesizable Architecture and Agile Design Space Exploration
by: Zhang, Haoyi, et al.
Published: (2024)

UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
by: Ye, Junhao, et al.
Published: (2026)

A Novel HDL Code Generator for Effectively Testing FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2024)

FormalRTL: Verified RTL Synthesis at Scale
by: Li, Kezhi, et al.
Published: (2026)

Structural Mutation Based Differential Testing for FPGA Logic Synthesis Compilers
by: Xu, Zhihao, et al.
Published: (2025)

A Vertically Integrated Framework for Templatized Chip Design
by: Kim, Jeongeun, et al.
Published: (2025)

Exploring Code Language Models for Automated HLS-based Hardware Generation: Benchmark, Infrastructure and Analysis
by: Gai, Jiahao, et al.
Published: (2025)

FLAG: Formal and LLM-assisted SVA Generation for Formal Specifications of On-Chip Communication Protocols
by: Shih, Yu-An, et al.
Published: (2025)

LeGend: A Data-Driven Framework for Lemma Generation in Hardware Model Checking
by: Miao, Mingkai, et al.
Published: (2026)

AnalogMaster: Large Language Model-based Automated Analog IC Design Framework from Image to Layout
by: Qin, Xian Rong, et al.
Published: (2026)

A High-level Synthesis Toolchain for the Julia Language
by: Short, Benedict, et al.
Published: (2025)

VFocus: Better Verilog Generation from Large Language Model via Focused Reasoning
by: Zhao, Zhuorui, et al.
Published: (2025)

A Survey: Collaborative Hardware and Software Design in the Era of Large Language Models
by: Guo, Cong, et al.
Published: (2024)

AnalogGym: An Open and Practical Testing Suite for Analog Circuit Synthesis
by: Li, Jintao, et al.
Published: (2024)

Selective Parallel Loading of Large-Scale Compressed Graphs with ParaGrapher
by: Esfahani, Mohsen Koohi, et al.
Published: (2024)

Customizing a Large Language Model for VHDL Design of High-Performance Microprocessors
by: Dupuis, Nicolas, et al.
Published: (2025)

ITHICA: Intra-Thread Instruction Checking Approach for Defect-Induced Silent Data Corruptions
by: Vavelidou, Ioanna, et al.
Published: (2026)

Using LLMs to Facilitate Formal Verification of RTL
by: Orenes-Vera, Marcelo, et al.
Published: (2023)

Offloading Data Center Tax
by: Revankar, Akshay, et al.
Published: (2025)

EquivFusion: Unifying Hardware Equivalence Checking from Algorithms to Netlists via MLIR
by: Zhu, Jiaying, et al.
Published: (2026)

Quantifying Uncertainty in FMEDA Safety Metrics: An Error Propagation Approach for Enhanced ASIC Verification
by: Armato, Antonino, et al.
Published: (2026)

Scalable Software Testing in Fast Virtual Platforms: Leveraging SystemC, QEMU and Containerization
by: Jünger, Lukas, et al.
Published: (2025)

AnalogSeeker: An Open-source Foundation Language Model for Analog Circuit Design
by: Chen, Zihao, et al.
Published: (2025)

RTLRewriter: Methodologies for Large Models aided RTL Code Optimization
by: Yao, Xufeng, et al.
Published: (2024)

The Argument for Meta-Modeling-Based Approaches to Hardware Generation Languages
by: Schreiner, Johannes, et al.
Published: (2024)

AnalogTester: A Large Language Model-Based Framework for Automatic Testbench Generation in Analog Circuit Design
by: Chen, Weiyu, et al.
Published: (2025)

DRCY: Agentic Hardware Design Reviews
by: Dumont, Kyle, et al.
Published: (2026)

FALCON: An ML Framework for Fully Automated Layout-Constrained Analog Circuit Design
by: Mehradfar, Asal, et al.
Published: (2025)

DUET: Agentic Design Understanding via Experimentation and Testing
by: Smith, Gus Henry, et al.
Published: (2025)

RTLSquad: Multi-Agent Based Interpretable RTL Design
by: Wang, Bowei, et al.
Published: (2025)

AutoFlows++: Hierarchical Message Flow Mining for System on Chip Designs
by: Nadimi, Bardia, et al.
Published: (2026)

Using LLM such as ChatGPT for Designing and Implementing a RISC Processor: Execution,Challenges and Limitations
by: Hossain, Shadeeb, et al.
Published: (2024)

A Semi-Formal Verification Methodology for Efficient Configuration Coverage of Highly Configurable Digital Designs
by: Kumar, Aman, et al.
Published: (2024)

Veri-Sure: A Contract-Aware Multi-Agent Framework with Temporal Tracing and Formal Verification for Correct RTL Code Generation
by: Liu, Jiale, et al.
Published: (2026)

GreenMalloc: Allocator Optimisation for Industrial Workloads
by: Dakhama, Aidan, et al.
Published: (2025)

Bridging the Gap: Physical PCI Device Integration Into SystemC-TLM Virtual Platforms
by: Bosbach, Nils, et al.
Published: (2025)